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Product Datasheet
7
82571EB/82572EI Gigabit Ethernet Controller
2.5
Manageability Features
2.6
Additional Device Features
Features
Benefits
Manageability features:
Two SMBus ports one with Fast Management Link
Capability
Alerting Standards Format 1.0 and 2.0
Advanced Power Management (Wake on LAN)
Alerting and control via standardized interfaces
Network management flexibility
Manageability data transfers up to 8 Mb/s peak rate
On-board microcontroller
Enables effective ASF 2.0 implementations
Promotes customized designs
Allows packets routing to and from either LAN port
and a server management processor
Supports serial text and keyboard redirection
Supports remote floppy/CD
Preboot eXecution Environment (PXE) Flash interface
support (32-bit nd 64-bit)
Local Flash interface for PXE image
Compliance with PCI Power Management 1.1 and ACPI
2.0 register set compliant including:
D0 and D3 power states
Network Device Class Power Management
Specification 1.1
PCI power management capability requirements for PC
and embedded applications
SNMP and RMON statistic counters
Easy system monitoring with industry standard
consoles
SDG 3.0, WfM 3.0, and PC2001 compliance
Remote network management capabilities through
DMI 2.0 and SNMP software
Wake on LAN support
Packet recognition and wake-up for NIC and LOM
applications without software configuration
Features
Benefits
82571EB: Two complete Gigabit Ethernet connections in a
single device
Inherent dual port teaming ability
High availability using one port for failover
Higher throughput than single Gigabit Ethernet port
Lower latency due to one electrical load on the bus
Saves critical board space
Reduced multi-port Gigabit Ethernet costs
Integrated SERDES
Supports backplane and fiber applications as well as
copper-based Gigabit
Four activity and link indication outputs (per port) that
directly drive LEDs
Link and activity indications (10, 100, and 1000 Mbps)
on each port
Programmable LED functionality
Software definable function (speed, link, and activity)
and blinking allowing flexible LED implementations
Internal PLL for clock generation can use a 25 MHz crystal
Lower component count and system cost