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參數(shù)資料
| 型號： | 82572EI |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Gigabit Ethernet Controller |
| 中文描述： | 1 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, BGA256 |
| 封裝： | 17 X 17 MM, FC-BGA-256 |
| 文件頁數(shù)： | 20/58頁 |
| 文件大小： | 318K |
| 代理商： | 82572EI |
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82571EB/82572EI Gigabit Ethernet Controller
14
Product Datasheet
3.10
Serializer / Deserializer Signals
3.11
Test Interface Signals
Symbol
Type
Name and Function
SRDSI_0_PLUS
SRDSI_0_MINUS
SRDSI_1_PLUS/
RSVD_M16
SRDSI_1_MINUS/
RSVD_L16
A(I)
SERDES Receive Pairs.
Signals SRDSI_0_PLUS and SRDSI_0_MINUS make the
differential receive pair for the 1.25 GHz serial interface for Port 0. For serializer/
deserializer operation, the inputs should be coupled to ECL voltage levels.
Signals SRDSI_1_PLUS and SRDSI_1_MINUS make the differential receive pair for
the 1.25 GHz serial interface for Port 1. For serializer/deserializer operation, the inputs
should be coupled to ECL voltage levels.
If the SERDES interface is not used, these pins should not be connected.
SRDSO_0_PLUS
SRDSO_0_MINUS
SRDSO_1_PLUS/
RSVD_K15
SRDSO_1_MINUS
/RSVD_L15
A(O)
SERDES Transmit Pairs.
Signals SRDSO_0_PLUS and SRDSO_0_MINUS make the
differential transmit pair for the 1.25 GHz serial interface for Port 0. For serializer/
deserializer operation, the outputs drive the LVPECL voltage levels.
Signals SRDSO_1_PLUS and SRDSO_1_MINUS make the differential transmit pair for
the 1.25 GHz serial interface for Port 1. For serializer/deserializer operation, the outputs
drive the LVPECL voltage levels.
If the SERDES interface is not used, these pins should not be connected.
SRDSA_SIG_DET
SRDSB_SIG_DET/
RSVD_C4
I
Signal Detects.
These pins (SRDSA_SIG_DET for Port 0; SRDSB_SIG_DET for Port
1) indicate whether the SERDES signals (connected to the 1.25 GHz serial interface)
have been detected by the optical transceivers. If the SERDES interface is not used, the
SIG_DET inputs can be left unconnected.
SRDS_RCOMPp
SRDS_RCOMPn
A
SERDES Impedance Compensation.
Connect the recommended resistor value across
these balls, even if not using the SERDES interface. Refer to the 82571EB/82572EI
Design Guide for the recommended value.
Symbol
Type
Name and Function
JTCK
I
JTAG Test Access Port Clock.
JTDI
I
JTAG Test Access Port Test Data In.
JTDO
O
JTAG Test Access Port Test Data Out.
JTMS
I
JTAG Test Access Port Mode Select.
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