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參數(shù)資料
| 型號： | 82C900 |
| 廠商： | SIEMENS AG |
| 英文描述： | Standalone TwinCAN Controller(獨立 雙CAN控制器) |
| 中文描述： | 獨立TwinCAN控制器（獨立雙的CAN控制器） |
| 文件頁數(shù)： | 13/29頁 |
| 文件大?。?/td> | 488K |
| 代理商： | 82C900 |
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82C900
Data Sheet
13
V 1.0D3, 2001-03
Preliminary
MODE1
25
I/O,
open
drain
Interface Mode Selection
Pin MODE1 determines the access mode of the host
device.
MODE0=0:
8-bit multiplexed bus
MODE1=0: Infineon / Intel mode, (RD, WR)
MODE1=1: Motorola mode, (R/W, E)
MODE0=1:
On-chip SSC
MODE1=0: SSC is slave, host device is master
MODE1=1: SSC is master, external serial
EEPROM is slave
After registering the initial state of MODE1 with the rising
edge of the reset signal, the respective pin can be used
as additional general purpose or special function I/O line
according register IOMODE4.
XTAL1
Input of the inverting oscillator amplifier and input to the
internal clock generation circuit.
When the 82C900 device is provided with an external
clock, XTAL1 should be driven while XTAL2 is left
unconnected.
Minimum and maximum high and low pulse width as well
as rise/fall times specified in the AC characteristics must
be respected.
XTAL2
Output of the inverting oscillator amplifier.
Ground
, both pins must be connected.
Power Supply
, both pins must be connected.
XTAL1
4
I
XTAL2
5
O
V
SS
V
DD
21, 8
22, 7
0V
+5V
1)
The slew rate of the output pins OUT0, OUT1, CTRL1..3, P0..P7, TXDCA and TXDCB can be defined by the
bit fields SLR0..3 in register GLOBCTR.
2)
After reset, this pin is configured as clock output, see register CLKCTR.
3)
The initial logic state on pins MODE0 and MODE1 is registered with the rising edge of the RESET input.
Afterwards, both pins can be used as additional I/O lines, according to functionality specified in register
IOMODE4.
Table 1
Symbol
Pin Definitions and Functions
(cont
’
d)
Pin
Number
I/O
1)
Function
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