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82C900
Data Sheet
15
V 1.0D3, 2001-03
Preliminary
CAN Node A Global Int. Node Pointer Reg.
CAN Node A Frame Counter Register
CAN Node A INTID Mask Register 0
CAN Node A INTID Mask Register 4
CAN Node A Error Counter Register
TwinCAN Kernel, Node B Registers
CAN Node B Control Register
CAN Node B Status Register
CAN Node B Interrupt Pending Register
CAN Node B Bit Timing Register
CAN Node B Global Int. Node Pointer Reg.
CAN Node B Frame Counter Register
CAN Node B INTID Mask Register 0
CAN Node B INTID Mask Register 4
CAN Node B Error Counter Register
TwinCAN Kernel, Message Object Registers
CAN Message Object n Data Register 0
AGINP
AFCR
AIMR0
AIMR4
AECNT
0210
H
0214
H
0218
H
021C
H
0220
H
0000 0000
H
0000 0000
H
0000 0000
H
0000 0000
H
0060 0000
H
BCR
BSR
BIR
BBTR
BGINP
BFCR
BIMR0
BIMR4
BECNT
0240
H
0244
H
0248
H
024C
H
0250
H
0254
H
0258
H
025C
H
0260
H
0000 0001
H
0000 0000
H
0000 0000
H
0000 0000
H
0000 0000
H
0000 0000
H
0000 0000
H
0000 0000
H
0060 0000
H
MSGDRn0
0300
H
+ n*20
H
0304
H
+ n*20
H
0308
H
+ n*20
H
030C
H
+ n*20
H
0310
H
+ n*20
H
0314
H
+ n*20
H
0318
H
+ n*20
H
0000 0000
H
CAN Message Object n Data Register 4
MSGDRn4
0000 0000
H
CAN Message Object n Arbitration Register MSGARn
0000 0000
H
CAN Message Object n Acceptance Mask
Register
CAN Message Object n Message Control
Register
CAN Message Object n Message
Configuration Register
CAN Message Object n Gateway / FIFO
Control Register
MSGAMRn
FFFF FFFF
H
MSGCTRn
0000 5555
H
MSGCFGn
0000 0000
H
MSGFGCRn
0000 0000
H
1)
Registers with 32-bit reset values are located in the CAN RAM and have to be accessed accordingly. The
other registers are standard SFRs, which have 16-bit reset values.
Table 0-1
Register Name
Summary of Registers
(cont
’
d)
Register
Symbol
Address
Reset Value
1)