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參數(shù)資料
| 型號： | 8346BLDCQETD |
| 英文描述： | Targeting Document for the 56F8346 BLDC Motor Control Application with Quadrature Encoder |
| 中文描述： | 配置文件與正交編碼器的56F8346無刷直流電機(jī)控制中的應(yīng)用 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 490K |
| 代理商： | 8346BLDCQETD |
Hardware Set-up
8
3-Phase BLDC Motor Control with Quadrature Encoder
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Figure 2-4. 56F8346EVM Jumper Reference
Table 2-1. 56F8346EVM Jumper Settings
Jumper
Group
Comment
Connections
JG1
Use on-board EXTAL crystal input for CPU oscillator
1-2
JG2
Use on-board XTAL crystal input for CPU oscillator
1-2
JG3
Enable Internal Boot Mode
1-2
JG4
Enable A0 - A19 for external memory accesses
NC
JG5
Enable SRAM Memory Bank 0 (use CS0)
1-2
JG6
Enable SRAM Memory Bank 1 (use CS1 & CS2)
1-2, 3-4
JG7
Enable RS-232 Disable
NC
JG8
SPI #0 Daisy Chain (Optional--not populated on board by default)
NC
JG9
Enable on-board Parallel JTAG Host/Target Interface
NC
JG10
Connect Analog Ground to Digital Ground
NC
JG11
CAN termination selected
1-2
JG12
Pass RXD0 & TXD0 to RS-232 level converter
1-2, 3-4
JG13
Enable Crystal Mode
1-2
JG14
Pass Temperature Diode to ANA7
1-2
JG15
User Jumper #0
1-2
JG16
User Jumper #1
1-2
JG3
DSP56F836EVM
U4
J3
JTAG
P2
S
LED3
P1
Y1
U1
U2
S2
S1
S3
P3
PC0
PC1
PC2
PC3
PD6
PD7
PWMA0
PWMA1
PWMA2
PWMA3
PWMA4
PWMA5
JG2
JG5
U11
RESET
IRQB
IRQA
1
2
JG12
JG4
JG10
JG9
JG1
JG15
JG7
JG14
JG12
1
JG15
3
JG7
U3
U10
JG13
JG3
JG4
JG11
JG6
J5
J6
JG16
J13
J12
J8
J7
J2
J1
J10
J11
J9
J15
J16
J21
J14
J17
J18
J19
J20
JG14
1
JG13
2
1
JG16
3
3
4
1
JG1
3
JG2
JG9
JG10
1
2
JG6
3
4
JG11
JG5
F
Freescale Semiconductor, Inc.
n
.
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