參數(shù)資料
型號(hào)： 853S314AGILFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 853S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封裝： 4.40 MM X 6.50 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20
文件頁(yè)數(shù)： 1/16頁(yè)
文件大?。?/td> 282K
代理商： 853S314AGILFT
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-2.5V,
3.3V LVPECL/ECL FANOUT BUFFER
ICS853S314I
IDT / ICS 3.3V, 2.5V LVPECL/ECL FANOUT BUFFER
1
ICS853S314AFI REV. A JANUARY 24, 2009
GENERAL DESCRIPTION
The ICS853S314I is a low skew 1-to-4 Differential
Fanout Buffer, designed with clock distribution in
mind, accepting two clock sources into an input
MUX. The MUX is controlled by a CLK_SEL pin.
This makes the ICS853S314I very versatile, in that,
it can operate as both a differential clock buffer as well as a
signal-level translator and fanout buffer.
The device is designed on a SiGe process and can operate at
frequencies in excess of 2.7GHz. This ensures negligible jitter
introduction to the timing budget which makes it an ideal choice
for distributing high frequency, high precision clocks across
back planes and boards in communication systems. Internal
temperature compensation guarantees consistent performance
across various platforms.
FEATURES
Four differential ECL/LVPECL level outputs
One differential ECL/LVPECL or single-ended input (CLKA)
One differential HSTL or single-ended input (CLKB)
Maximum output frequency: 2.7GHz
Additive phase jitter, RMS: 0.138ps (typical) @ 156.25MHz,
Output skew: 50ps (maximum)
Part-to-part skew: 150ps (maximum)
LVPECL and HSTL mode operating voltage supply range:
V
CC = 2.5V±5% or 3.3V±5%, VEE = 0V
ECL mode operating voltage supply range:
V
EE = -3.3V±5% or -2.5V±5%, VCC = 0V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
HiPerClockS
ICS
ICS853S314I
20-Lead, 209-MIL SSOP
5.30mm x 7.20mm x 1.75mm body package
F Package
Top View
20-Lead TSSOP
4.4mm x 6.5mm x 0.925mm body package
G Package
Top View
VCC
nc
VCC
CLK_SEL
CLKA
nCLKA
CLKB
nCLKB
VEE
VCC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
VCC
0
1
V
CC
V
CC
V
EE
V
EE
V
EE
CLKA
nCLKA
CLKB
nCLKB
CLK_SEL
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
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