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參數(shù)資料
| 型號： | 873034AGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 873034 SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 4.40 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, TSSOP-16 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 298K |
| 代理商： | 873034AGLFT |
873034AM
7
REV. A JANUARY 17, 2008
ICS873034
LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
APPLICATION INFORMATION
FIGURE 2A. SINGLE ENDED LVCMOS SIGNAL DRIVING DIFFERENTIAL INPUT
Figure 2A shows an example of the differential input that
can be wired to accept single ended LVCMOS levels. The
reference voltage level V
BB generated from the device is
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS
connected to the negative input. The C1 capacitor should
be located as close as possible to the input pin.
FIGURE 2B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
Figure 2B shows an example of the differential input that
can be wired to accept single ended LVPECL levels. The
reference voltage level V
BB generated from the device is
connected to the negative input.
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
VCC
R2
1K
V_REF
C1
0.1u
R1
1K
Single Ended Clock Input
PCLK
nPCLK
PCLK
nPCLK
VBB
C1
0.1u
CLK_IN
VCC
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