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參數(shù)資料
| 型號： | 873996AYLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 873996 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026ABC-HD, TQFP-48 |
| 文件頁數(shù)： | 1/21頁 |
| 文件大?。?/td> | 352K |
| 代理商： | 873996AYLF |
DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY/MULTIPLIER/DIVIDER
ICS873996
IDT / ICS 3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER
1
ICS873996AY REV. A FEBRUARY 19, 2008
GENERAL DESCRIPTION
The ICS873996 is a Zero Delay/Multiplier/Divider
with hitless input clock switching capability and a
member of the HiPerClockS family of low jitter/
phase noise devices from IDT. The ICS873996 is
ideal for use in redundant, fault tolerant clock trees
where low phase noise and low jitter are critical. The device
receives two differential LVPECL clock signals from which it
generates 6 LVPECL clock outputs with “zero” delay. The output
divider and feedback divider selections also allow for frequency
multiplication or division.
The ICS873996 Dynamic Clock Switch (DCS) circuit
continuously monitors both input clock signals. Upon detection
of a failure (input clock stuck LOW or HIGH for at least 1 period),
INP_BAD for that clock will be set HIGH. If that clock is the
primary clock, the DCS will switch to the good secondary clock
and phase/frequency alignment will occur with minimal output
phase disturbance.
The low jitter characteristics combined with input clock monitor-
ing and automatic switching from bad to good input clocks make
the ICS873996 an ideal choice for mission critical applications
that utilize 1G or 10G Ethernet or 1G/4G/10G Fibre Channel.
HiPerClockS
ICS
FEATURES
Six differential 3.3V LVPECL outputs
Selectable differential clock inputs
CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Input clock frequency range: 49MHz to 213.33MHz
Output clock frequency range: 49MHz to 640MHz
VCO range: 490MHz to 640MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Output skew: 100ps (maximum)
RMS phase jitter (1.875MHz - 20MHz): 0.6ps (typical)
assuming a low phase noise reference clock input
3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
nMR
NA[2:0]
000 ÷1
001 ÷2
010 ÷3
011 ÷4
100 ÷5
101 ÷6
110 ÷8
111 ÷10(default)
NB[2:0]
000 ÷1
001 ÷2
010 ÷3
011 ÷4
100 ÷5
101 ÷6
110 ÷8
111 ÷10(default)
NFB[2:0]
000 Reserved
001 Reserved
010 ÷3
011 ÷4
100 ÷5
101 ÷6
110 ÷8
111 ÷10(default)
nMR
Dynamic Switch
Logic
Phase
Detector
0
1
VCO
490MHz - 640MHz
3
0
1
PIN ASSIGNMENT
V
CC
NB0
NB1
NB2
V
EE
NA0
NA1
NA2
V
CCO
_
B
nQB2
QB2
nQB1
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
PLL_SEL
nMR
nINIT
VEE
CLK0
nCLK0
CLK1
nCLK1
EXT_FB
nEXT_FB
SEL_CLK
BW
VCCO_A
QA0
nQA0
QA1
nQA1
QA2
nQA2
VCCO_A
VCCO_B
QB0
nQB0
QB1
MAN_O
VERRIDE
V
CC
INP1BAD
INP0BAD
CLK_INDICA
T
O
R
NFB2
NFB1
NFB0
V
CCA
nQFB
QFB
V
CCO
_
FB
48-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm
package body
Y Package
Top View
ICS873996
NA[2:0]
PLL_SEL
CLK_INDICATOR
INP1BAD
INP0BAD
nINIT
SEL_CLK
MAN_OVERRIDE
CLK0
nCLK0
CLK1
nCLK1
EXT_FB
nEXT_FB
BW
NB[2:0]
NFB[2:0]
QA0
nQA0
QA1
nQA1
QA2
nQA2
QB0
nQB0
QB1
nQB1
QB2
nQB2
QFB
nQFB
BLOCK DIAGRAM
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 873996AYLFT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 873996AYT | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Multiplier Single 48-Pin TQFP EP T/R 制造商:Integrated Device Technology Inc 功能描述:873996AYT - Tape and Reel |
| 873D | 制造商:Datak Corporation 功能描述: |
| 873DB | 制造商:Datak Corporation 功能描述:Conn TNC M 50Ohm Crimp ST Cable Mount Nickel Bulk |
| 873DPO-G1 | 制造商:Edwards Signaling & Security Systems 功能描述:HORN 24VDC DOUBLE PROJECTOR |
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