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參數(shù)資料
| 型號： | 8832I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16-Bit, Ultra-Low Power, Voltage-Output Digital-to-Analog Converter |
| 中文描述： | 16位，超低功耗，電壓輸出數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 7/26頁 |
| 文件大?。?/td> | 702K |
| 代理商： | 8832I |
www.ti.com
TIMING CHARACTERISTICS: V
DD
= +5 V
(1)(2)
At –40
°
C to +85
°
C, unless otherwise noted.
TIMING CHARACTERISTICS: V
DD
= +3 V
(1)(2)
At –40
°
C to +85
°
C, unless otherwise noted.
DAC8832
SBAS380A–FEBRUARY 2006–REVISED APRIL 2006
PARAMETER
MIN
20
10
10
10
10
10
30
10
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
t
sck
t
wsck
t
Delay
t
Lead
t
Lag
t
DSCLK
t
td
t
su
t
ho
t
WLDAC
t
DLDAC
SCLK period
SCLK high or low time
Delay from SCLK high to CS low
CS enable lead time
CS enable lag time
Delay from CS high to SCLK high
CS high between active period
Data setup time (input)
Data hold time (input)
LDAC width
Delay from CS high to LDAC low
V
DD
high to CS low (power-up delay)
0
30
30
10
(1)
(2)
Assured by design. Not production tested.
Sample tested during the initial release and after any redesign or process changes that may affect this parameter.
PARAMETER
MIN
20
10
10
10
10
10
30
10
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
t
sck
t
wsck
t
Delay
t
Lead
t
Lag
t
DSCLK
t
td
t
su
t
ho
t
WLDAC
t
DLDAC
SCLK period
SCLK high or low time
Delay from SCLK high to CS low
CS enable lead time
CS enable lag time
Delay from CS high to SCLK high
CS high between active period
Data setup time (input)
Data hold time (input)
LDAC width
Delay from CS high to LDAC low
V
DD
high to CS low (power-up delay)
0
30
30
10
(1)
(2)
Assured by design. Not production tested.
Sample tested during the initial release and after any redesign or process changes that may affect this parameter.
7
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