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參數(shù)資料
| 型號： | 89C1051 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 151K |
| 代理商： | 89C1051 |
AT89C1051
4-8
Programming Algorithm:
To program the AT89C1051,
the following sequence is recommended.
1. Power-up sequence:
Apply power between V
CC
and GND pins
Set RST and XTAL1 to GND
2. Set pin RST to ‘H’
Set pin P3.2 to ‘H’
3. Apply the appropriate combination of ‘H’ or ‘L’ logic
levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the
programming operations shown in the PEROM Pro-
gramming Modes table.
To Program and Verify the Array:
4. Apply data for Code byte at location 000H to P1.0 to
P1.7.
5. Raise RST to 12V to enable programming.
6. Pulse P3.2 once to program a byte in the PEROM array
or the lock bits. The byte-write cycle is self-timed and
typically takes 1.2 ms.
7. To verify the programmed data, lower RST from 12V to
logic ‘H’ level and set pins P3.3 to P3.7 to the appropiate
levels. Output data can be read at the port P1 pins.
8. To program a byte at the next address location, pulse
XTAL1 pin once to advance the internal address counter.
Apply new data to the port P1 pins.
9. Repeat steps 5 through 8, changing data and advancing
the address counter for the entire 1K byte array or until
the end of the object file is reached.
10.Power-off sequence:
set XTAL1 to ‘L’
set RST to ‘L’
Turn V
CC
power off
Flash Programming Modes
Data Polling:
The AT89C1051 features Data Polling to
indicate the end of a write cycle. During a write cycle, an
attempted read of the last byte written will result in the com-
plement of the written data on P1.7. Once the write cycle
has been completed, true data is valid on all outputs, and
the next cycle may begin. Data Polling may begin any time
after a write cycle has been initiated.
Ready/Busy:
The Progress of byte programming can also
be monitored by the RDY/BSY output signal. Pin P3.1 is
pulled low after P3.2 goes High during programming to indi-
cate BUSY. P3.1 is pulled High again when programming is
done to indicate READY.
Program Verify:
If lock bits LB1 and LB2 have not been
programmed code data can be read back via the data lines
for verification:
1. Reset the internal address counter to 000H by bringing
RST from ’L’ to ’H’.
2. Apply the appropriate control signals for Read Code data
and read the output data at the port P1 pins.
3. Pulse pin XTAL1 once to advance the internal address
counter.
4. Read the next code data byte at the port P1 pins.
5. Repeat steps 3 and 4 until the entire array is read.
The lock bits cannot be verified directly. Verification of the
lock bits is achieved by observing that their features are
enabled.
Note:
1. The internal PEROM address counter is reset to 000H on the rising edge of RST and is advanced by a positive pulse at
XTAL1 pin.
2. Chip Erase requires a 10-ms PROG pulse.
3. P3.1 is pulled Low during programming to indicate RDY/BSY.
Mode
RST/VPP
P3.2/PROG
P3.3
P3.4
P3.5
P3.7
Write Code Data
(1)(3)
12V
L
H
H
H
Read Code Data
(1)
H
H
L
L
H
H
Write Lock
Bit-1
12V
H
H
H
H
Bit-2
12V
H
H
L
L
Chip Erase
12V
H
L
L
L
Read Signature Byte
H
H
L
L
L
L
(2)
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