參數(shù)資料
型號(hào): 92HD206DX5PRGXYYX8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 編解碼器
英文描述: PCM CODEC, PQFP48
封裝: ROHS COMPLIANT, LQFP-48
文件頁數(shù): 107/176頁
文件大小: 1463K
代理商: 92HD206DX5PRGXYYX8
92HD206
8-CHANNEL HIGH DEFINITION AUDIO CODEC
PC AUDIO
IDT
8-CHANNEL HIGH DEFINITION AUDIO CODEC
36
92HD206
V 1.2 112006
IDT CONFIDENTIAL
6.2.14. AFG GPIOEn
[1]
Data1
RW
0x0
Data for GPIO1. If this GPIO bit is
configured as Sticky (edge-sensitive) input,
it can be cleared by writing zero (one) here
when the corresponding Polarity Control bit
is zero (one).
[0]
Data0
RW
0x0
Data for GPIO0. If this GPIO bit is
configured as Sticky (edge-sensitive) input,
it can be cleared by writing zero (one) here
when the corresponding Polarity Control bit
is zero (one).
Table 37. AFG GPIOEn Command Verb Format
Verb ID
Payload
Response
Get
F16
00
See bitfield table.
Set1
716
See bits [7:0] of bitfield table.
0000_0000h
Table 38. AFG GPIOEn Command Response Format
Bit
Bitfield Name
RW
Reset
Description
[31:5]
Rsvd
R
0x0
Reserved
[4]
Rsvd
RW
0x0
Reserved
[3]
Rsvd
RW
0x0
Reserved
[2]
Mask2
RW
0x0
Enable for GPIO2:
0 = pin is disabled (Hi-Z state);
1 = pin is enabled; behavior determined by
GPIO Direction control
[1]
Mask1
RW
0x0
Enable for GPIO1:
0 = pin is disabled (Hi-Z state);
1 = pin is enabled; behavior determined by
GPIO Direction control
[0]
Mask0
RW
0x0
Enable for GPIO0:
0 = pin is disabled (Hi-Z state);
1 = pin is enabled; behavior determined by
GPIO Direction control
Table 36. AFG GPIO Command Response Format
Bit
Bitfield Name
RW
Reset
Description
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