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參數(shù)資料
| 型號： | 930400801 |
| 廠商： | ATMEL CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 2304 CLBS, 40000 GATES, PQFP160 |
| 封裝： | MQFPF-160 |
| 文件頁數(shù)： | 11/43頁 |
| 文件大小： | 673K |
| 代理商： | 930400801 |
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AT40KEL040
4155H–AERO–02/06
connects on the diagonal inputs to the cell above and the cell below. It also connects to
the repeater of the cell above and below. In addition, each Secondary I/O also connects
into the busing network of the two nearest edge cells. This is an extremely powerful fea-
ture, as it provides logic cells toward the center of the array with fast access to I/Os via
local and express buses. It can be seen from the diagram that a given Secondary I/O
can be accessed from any logic cell on two rows or columns of the FPGA. See Figure
12a and Figure 13b.
Corner I/O
Logic cells at the corner of the FPGA array have direct-connect access to five separate
I/Os: 2 Primary, 2 Secondary and 1 Corner I/O. Corner I/Os are like an extra Secondary
I/O at each corner of the array. With the inclusion of Corner I/Os, an AT40KEL040
FPGA with n x n core cells always has 8n I/Os. As the diagram shows, Corner I/Os can
be accessed both from the corner logic cell and the horizontal and vertical busing net-
works running along the edges of the array. This means that many different edge logic
cells can access the Corner I/Os. See Figure 14.
相關PDF資料 |
PDF描述 |
|---|---|
| 930400802 | FPGA, 2304 CLBS, 40000 GATES, PQFP256 |
| 9305DMQB | 93 SERIES, ASYN POSITIVE EDGE TRIGGERED 4-BIT BINARY COUNTER, CDIP14 |
| 9308DMQB | 93 SERIES, DUAL LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP24 |
| 9308FMQB | 93 SERIES, DUAL LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDFP24 |
| 9309-00 | PRESCALER, UUC |
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