參數(shù)資料
型號(hào)： 930400801
廠商： ATMEL CORP
元件分類： FPGA
英文描述： FPGA, 2304 CLBS, 40000 GATES, PQFP160
封裝： MQFPF-160
文件頁(yè)數(shù)： 23/43頁(yè)
文件大?。?/td> 673K
代理商： 930400801
3
AT40KEL040
4155H–AERO–02/06
proven functions. The Automatic Component Generators work seamlessly with industry-
standard schematic and synthesis tools to create the fastest, most efficient designs
available.
The patented AT40KEL040 series architecture employs a symmetrical grid of small yet
powerful cells connected to a flexible busing network. Independently controlled clocks
and resets govern every column of cells. The array is surrounded by programmable I/O.
Devices offer 50,000 usable gates, and have 3,056 registers. AT40K series FPGAs uti-
lize a reliable 0.35 single-poly, 4-metal CMOS process and are 100% factory-tested.
Atmel’s PC- and workstation-based integrated development system (IDS) is used to cre-
ate AT40KEL040 series designs. Multiple design entry methods are supported.
The Atmel architecture was developed to provide the highest levels of performance,
functional density and design flexibility in an FPGA. The cells in the Atmel array are
small, efficient and can implement any pair of Boolean functions of (the same) three
inputs or any single Boolean function of four inputs. The cell’s small size leads to arrays
with large numbers of cells, greatly multiplying the functionality in each cell. A simple,
high-speed busing network provides fast, efficient communication over medium and
long distances.
AT40KEL040
Configurator
Statistics extracted from configuration bitstreams show that the maximum needed size
is 1Mbit.
In order to keep the maximum number of pins assigned to signals, it is recommended to
use a serial configuration interface.
This is the reason why Atmel proposes a 1Mbit serial EEPROM for configuring the
AT40KEL040, the AT17LV010-10DP which is also a 3.3V bias chip. It is packaged into a
28-pin DIL Flat Pack 400mils wide.
This memory has been tested for total dose under bias and unbiased conditions, exhib-
iting far better results when unbiased; this is the reason why it is recommended to switch
off the memory when it is not in the configuration mode.
In addition, heavy ions tests have shown that the data stored in the memory cells are not
corrupted eventhough errors may be detected while downloading the bitstream; this is
the result of the data serialization from the parallel memory plan; therefore, it is recom-
mended to use the FPGA CRC while configuring it, and to resume the configuration
when an error is detected.
相關(guān)PDF資料
PDF描述
930400802 FPGA, 2304 CLBS, 40000 GATES, PQFP256
9305DMQB 93 SERIES, ASYN POSITIVE EDGE TRIGGERED 4-BIT BINARY COUNTER, CDIP14
9308DMQB 93 SERIES, DUAL LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP24
9308FMQB 93 SERIES, DUAL LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDFP24
9309-00 PRESCALER, UUC
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