參數(shù)資料
型號： 933373600005
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC
封裝： WAFER
文件頁數(shù)： 6/10頁
文件大小： 104K
代理商： 933373600005
January 1995
5
Philips Semiconductors
Product specication
Dual D-type ip-op
HEF4013B
ip-ops
AC CHARACTERISTI CS
VSS =0V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYP.
MAX.
Set-up time
5
40
20
ns
see also waveforms
Figs 4 and 5
D
→ CP
10
tsu
25
10
ns
15
5
ns
Hold time
5
20
0
ns
D
→ CP
10
thold
20
0
ns
15
0
ns
Minimum clock
5
60
30
ns
pulse width; LOW
10
tWCPL
30
15
ns
15
20
10
ns
Minimum SD pulse
5
50
25
ns
width; HIGH
10
tWSDH
24
12
ns
15
20
10
ns
Minimum CD pulse
5
50
25
ns
width; HIGH
10
tWCDH
24
12
ns
15
20
10
ns
Recovery time
5
15
5ns
for SD
10
tRSD
15
0
ns
15
0
ns
Recovery time
5
40
25
ns
for CD
10
tRCD
25
10
ns
15
25
10
ns
Maximum clock
5
7
14
MHz
pulse frequency
10
fmax
14
28
MHz
15
20
40
MHz
VDD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
850 fi +∑ (foCL) × VDD 2
where
dissipation per
10
3 600 fi +∑ (foCL) × VDD 2
fi = input freq. (MHz)
package (P)
15
9 000 fi +∑ (foCL) × VDD 2
fo = output freq. (MHz)
CL = total load cap. (pF)
∑ (f
oCL) = sum of outputs
VDD = supply voltage (V)
相關(guān)PDF資料
PDF描述
933372660653 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
933372660652 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
933277610652 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
935230510528 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQFP44
933968320512 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44
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