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參數(shù)資料
| 型號： | 933493470112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)器 |
| 英文描述： | 4000/14000/40000 SERIES, ASYN POSITIVE EDGE TRIGGERED 17-BIT UP DECADE COUNTER, CDIP18 |
| 封裝： | CERAMIC, DIP-18 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 63K |
| 代理商： | 933493470112 |
January 1995
8
Philips Semiconductors
Product specication
Quadruple static decade counters
HEF4737B
HEF4737V
Output transition
5
35
70
ns
15 ns
+ (0,40 ns/pF) CL
times; any output
10
tTHL
18
36
ns
9 ns
+ (0,18 ns/pF) CL
HIGH to LOW
15
30
ns
8 ns
+ (0,13 ns/pF) CL
5
50
100
ns
15 ns
+ (0,70 ns/pF) CL
LOW to HIGH
10
tTLH
30
60
ns
13 ns
+ (0,33 ns/pF) CL
15
25
50
ns
13 ns
+ (0,23 ns/pF) CL
3-state propagation delays
Output disable times
EO
→ O
n
5
60
120
ns
HIGH
10
tPHZ
35
70
ns
15
25
50
ns
5
60
120
ns
LOW
10
tPLZ
35
70
ns
15
25
50
ns
Output enable times
EO
→ O
n
5
90
180
ns
HIGH
10
tPZH
40
80
ns
15
30
60
ns
5
90
180
ns
LOW
10
tPZL
40
80
ns
15
30
60
ns
Maximum CP pulse
5
160
80
ns
width; LOW
10
tWCPL
60
30
ns
15
50
25
ns
Minimum MR pulse
5
100
50
ns
width; HIGH
10
tWMRH
50
25
ns
15
40
20
ns
Minimum PL pulse
5
120
60
ns
width; HIGH
10
tWPLH
60
30
ns
15
50
25
ns
Minimum T pulse
5
100
50
ns
width; HIGH
10
tWTH
40
20
ns
15
36
18
ns
Maximum clock
5
3
6
MHz
pulse frequency
10
fmax
8
16
MHz
15
10
20
MHz
VDD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
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