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參數(shù)資料
| 型號： | 933670070652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, MO-001AE, SOT-38-1, DIP-16 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 183K |
| 代理商： | 933670070652 |
1998 Jul 08
5
Philips Semiconductors
Product specication
Quad D-type ip-op with reset; positive-edge trigger
74HC/HCT175
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
CP to Qn, Qn
55
175
220
265
ns
2.0
Fig.6
20
35
44
53
4.5
16
30
37
45
6.0
tPHL/ tPLH
propagation delay
MR to Qn, Qn
50
150
190
225
ns
2.0
Fig.8
18
30
38
45
4.5
14
26
33
38
6.0
tTHL/ tTLH
output transition time
19
75
95
110
ns
2.0
Fig.6
7
15
19
22
4.5
6
13
16
19
6.0
tW
clock pulse width
HIGH or LOW
80
22
100
120
ns
2.0
Fig.6
16
8
20
24
4.5
14
6
17
20
6.0
tW
master reset pulse width
LOW
80
19
100
120
ns
2.0
Fig.8
16
7
20
24
4.5
14
6
17
20
6.0
trem
removal time
MR to CP
5
33
5
ns
2.0
Fig.8
5
12
5
4.5
5
10
5
6.0
tsu
set-up time
Dn to CP
80
3
100
120
ns
2.0
Fig.7
16
1
20
24
4.5
14
1
17
20
6.0
th
hold time
CP to Dn
25
2
30
40
ns
2.0
Fig.7
5
0
6
8
4.5
4
0
5
7
6.0
fmax
maximum clock pulse
frequency
6.0
25
4.8
4.0
MHz
2.0
Fig.6
30
75
24
20
4.5
35
89
28
24
6.0
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