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參數(shù)資料
| 型號(hào)： | 933670070652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, MO-001AE, SOT-38-1, DIP-16 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 183K |
| 代理商： | 933670070652 |
1998 Jul 08
7
Philips Semiconductors
Product specication
Quad D-type ip-op with reset; positive-edge trigger
74HC/HCT175
AC WAVEFORMS
Fig.6
Waveforms showing the clock (CP) to
outputs (Qn, Qn) propagation delays, the
clock pulse width, output transition times
and the maximum clock pulse frequency.
(1)
HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing the data set-up and
hold times for the data input (Dn).
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1)
HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.8
Waveforms showing the master reset (MR)
pulse width, the master reset to outputs
(Qn, Qn) propagation delays and the master
reset to clock (CP) removal time.
(1)
HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
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