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參數(shù)資料
| 型號(hào)： | 933714720653 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDSO16 |
| 封裝： | SOT-109, SO-16 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 132K |
| 代理商： | 933714720653 |
Philips Semiconductors - PIP - 74HC/HCT390; Dual decade ripple counter
Product Information
74HC/HCT390; Dual
decade ripple
counter
Information as of 2003-04-22
Stay informed
Download datasheet
Applications
Block diagram
topGeneral description
The 74HC/HCT390 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT390 are dual 4-bit decade ripple counters divided into four separately clocked sections. The counters
have two divide-by-2 sections and two divide-by-5 sections. These sections are normally used in a BCD decade or
bi-quinary configuration, since they share a common master reset input (nMR). If the two master reset inputs (1MR
and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are
possible within one package. The separate clocks (nCP0 and nCP1) of each section allow ripple counter or frequency
division applications of divide-by-2, 4, 5, 10, 20, 25, 50 or 100.
Each section is triggered by the HIGH-to-LOW transition of the clock inputs (nCP0 and nCP1). For BCD decade
operation, the nQ0 output is connected to the nCP1 input of, the divide-by-5 section. For bi-quinary decade
operation, the nQ3 output is connected to the nCP0 input and nQ0 becomes the decade output.
The master reset inputs (1MR and 2MR) are active HIGH asynchronous inputs to each decade counter which
operates on the portion of the counter identified by the '1' and '2' prefixes in the pin configuration. A HIGH level on
the nMR input overrides the clocks and sets the four outputs LOW.
topFeatures
q
Two BCD decade or bi-quinary counters
q
One package can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100
q
Two master reset inputs to clear each decade counter individually
q
Output capability: standard
q
ICC category: MSI
file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/74HC390N.html (1 of 4) [Apr-29-2003 2:02:40 PM]
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