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參數(shù)資料
| 型號： | 933714720653 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDSO16 |
| 封裝： | SOT-109, SO-16 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 132K |
| 代理商： | 933714720653 |
December 1990
2
Philips Semiconductors
Product specication
Dual decade ripple counter
74HC/HCT390
FEATURES
Two BCD decade or bi-quinary counters
One package can be configured to divide-by-2, 4, 5, 10,
20, 25, 50 or 100
Two master reset inputs to clear each decade counter
individually
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT390 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT390 are dual 4-bit decade ripple counters
divided into four separately clocked sections. The counters
have two divide-by-2 sections and two divide-by-5
sections. These sections are normally used in a BCD
decade or bi-quinary configuration, since they share a
common master reset input (nMR). If the two master reset
inputs (1MR and 2MR) are used to simultaneously clear all
8 bits of the counter, a number of counting configurations
are possible within one package. The separate clocks
(nCP0 and nCP1 ) of each section allow ripple counter or
frequency division applications of divide-by-2, 4, 5, 10, 20,
25, 50 or 100.
Each section is triggered by the HIGH-to-LOW transition of
the clock inputs (nCP0 and nCP1 ). For BCD decade
operation, the nQ0 output is connected to the nCP1 input
of, the divide-by-5 section. For bi-quinary decade
operation, the nQ3 output is connected to the nCP0 input
and nQ0 becomes the decade output.
The master reset inputs (1MR and 2MR) are active HIGH
asynchronous inputs to each decade counter which
operates on the portion of the counter identified by the “1”
and “2” prefixes in the pin configuration. A HIGH level on
the nMR input overrides the clocks and sets the four
outputs LOW.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CL = 15 pF; VCC =5V
nCP0 to nQ0
14
18
ns
nCP1 to nQ1
15
19
ns
nCP1 to nQ2
23
26
ns
nCP1 to nQ3
15
19
ns
nMR to Qn
16
18
ns
fmax
maximum clock frequency nCP0,nCP1
66
61
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per counter
notes 1 and 2
20
21
pF
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