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參數(shù)資料
| 型號： | 933715100652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)器 |
| 英文描述： | HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16 |
| 封裝： | SOT-109, SO-16 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 177K |
| 代理商： | 933715100652 |
December 1990
7
Philips Semiconductors
Product specication
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT193
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85 40 to +125
min.
typ.
max. min.
max.
min.
max.
tPHL/ tPLH
propagation delay
CPU,CPD to Qn
63
23
18
215
43
37
270
54
46
325
65
55
ns
2.0
4.5
6.0
Fig.7
tPHL/ tPLH
propagation delay
CPU to TCU
39
14
11
125
25
21
155
31
26
190
38
32
ns
2.0
4.5
6.0
Fig.8
tPHL/ tPLH
propagation delay
CPD to TCD
39
14
11
125
25
21
155
31
26
190
38
32
ns
2.0
4.5
6.0
Fig.8
tPHL/ tPLH
propagation delay
PL to Qn
69
25
20
220
44
37
275
55
47
330
66
56
ns
2.0
4.5
6.0
Fig.9
tPHL
propagation delay
MR to Qn
58
21
17
200
40
34
250
50
43
300
60
51
ns
2.0
4.5
6.0
Fig.10
tPHL/ tPLH
propagation delay
Dn to Qn
69
25
20
210
42
36
265
53
45
315
63
54
ns
2.0
4.5
6.0
Fig.9
tPHL/ tPLH
propagation delay
PL to TCU, PL to TCD
80
29
23
290
58
49
365
73
62
435
87
74
ns
2.0
4.5
6.0
Fig.12
tPHL/ tPLH
propagation delay
MR to TCU,MRto TCD
74
27
22
285
57
48
355
71
60
430
86
73
ns
2.0
4.5
6.0
Fig.12
tPHL/ tPLH
propagation delay
Dn to TCU,Dn to TCD
80
29
23
290
58
49
365
73
62
435
87
74
ns
2.0
4.5
6.0
Fig.12
tTHL/ tTLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.10
tW
up, down clock pulse
width HIGH or LOW
100
20
17
22
8
6
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.7
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