參數(shù)資料
型號(hào): 933715100652
廠商: NXP SEMICONDUCTORS
元件分類: 計(jì)數(shù)器
英文描述: HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16
封裝: SOT-109, SO-16
文件頁(yè)數(shù): 4/18頁(yè)
文件大?。?/td> 177K
代理商: 933715100652
December 1990
12
Philips Semiconductors
Product specication
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT193
Fig.10 Waveforms showing the master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU,
CPD removal time and output transition times.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3V; VI = GND to 3 V.
Fig.11 Waveforms showing the data input (Dn) to parallel load input (PL) set-up and hold times.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3V; VI = GND to 3 V.
Fig.12 Waveforms showing the data input (Dn), parallel load input (PL) and the master reset input (MR) to the
terminal count outputs (TCU, TCD) propagation delays.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3V; VI = GND to 3 V.
Fig.13 Waveforms showing the CPU to CPD or CPD to CPU hold times.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3V; VI = GND to 3 V.
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