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參數資料
| 型號： | 933798880652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 64 X 9 OTHER FIFO, 520 ns, PDSO28 |
| 封裝： | SO-28 |
| 文件頁數： | 4/8頁 |
| 文件大?。?/td> | 166K |
| 代理商： | 933798880652 |
December 1990
4
Philips Semiconductors
Product specication
9-bit x 64-word FIFO register; 3-state
74HC/HCT7030
PIN DESCRIPTION
Note
1. Pin 14 must be connected to GND. Pins 1 and 2 can be left floating or connected to GND, however it is not allowed
to let current flow in either direction between pins 1, 2 and 14.
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 2, 14
GND
ground (0 V)
3
DIR
data-in-ready output
4
SI
shift-in input (LOW-to-HIGH, edge-triggered)
5, 6, 7, 8, 9, 10, 11, 12, 13
D0 to D8
parallel data inputs
15
OE
output enable input (active LOW)
24, 23, 22, 21, 20, 19, 18, 17, 16
Q0 to Q8
3-state parallel data outputs
25
DOR
data-out-ready output
26
SO
shift-out input (HIGH-to-LOW, edge-triggered)
27
MR
asynchronous master-reset input (active LOW)
28
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
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