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參數(shù)資料
| 型號： | 933824060005 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 51K |
| 代理商： | 933824060005 |
December 1990
2
Philips Semiconductors
Product specication
Dual JK ip-op with reset; negative-edge trigger
74HC/HCT107
FEATURES
Output capability: standard
ICC category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT107 are dual negative-edge triggered
JK-type flip-flops featuring individual J, K, clock (nCP) and
reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to
the HIGH-to-LOW clock transition for predictable
operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing
the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CL = 15 pF;
VCC = 5 V
nCP to nQ
16
ns
nCP to nQ
1618ns
nR to nQ, nQ
1617ns
fmax
maximum clock frequency
78
73
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation
capacitance per ip-op
notes 1 and 2
30
pF
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