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參數(shù)資料
| 型號(hào)： | 933824060005 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC |
| 封裝： | DIE |
| 文件頁(yè)數(shù)： | 7/7頁(yè) |
| 文件大小： | 51K |
| 代理商： | 933824060005 |
December 1990
7
Philips Semiconductors
Product specication
Dual JK ip-op with reset; negative-edge trigger
74HC/HCT107
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”.
Fig.6
Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the J
and K to nCP set-up and hold times, the output transition times and the maximum clock pulse frequency.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays, the reset pulse width and
the nR to nCP removal time.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
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