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參數(shù)資料
| 型號： | 935007640602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14 |
| 封裝： | 0.300 INCH, PLASTIC, MO-001AA, SOT-27-1, DIP-14 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 100K |
| 代理商： | 935007640602 |
Philips Semiconductors
Product specification
74F50728
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
September 14, 1990
7
AC SETUP REQUIREMENTS
LIMITS
Tamb = +25°C
Tamb = 0°C to
+70
°C
Tamb = –40°C to +85°C
SYMBOL
PARAMETER
TEST
VCC = +5.0V
VCC = +5.0V ± 10%
UNIT
CONDITION
CL = 50pF,
RL = 500
CL = 50pF,
RL = 500
CL = 50pF,
RL = 500
MIN
TYP
MAX
MIN
MAX
MIN
MAX
tsu (H)
tsu(L)
Setup time, high or low
Dn to CPn
Waveform 1
1.5
2.0
ns
th (H)
th (L)
Hold time, high or low
Dn to CPn
Waveform 1
0.0
1.5
ns
tw (H)
tw (L)
CPn pulse width,
high or low
Waveform 2
3.0
4.0
3.5
5.0
4.0
5.5
ns
tw (L)
SDn, RDn pulse width, low
Waveform 2
4.5
4.0
4.5
ns
trec
Recovery time
SDn, RDn to CPn
Waveform 3
3.5
ns
AC WAVEFORMS
VM
CPn
VM
tsu(H)
th(H)
Jn, Kn
Qn
VM
tw(H)
1/fmax
tsu(L)
th(L)
VM
tPLH
Qn
tw(L)
tPHL
tPLH
SF00139
Waveform 1. Propagation delay for data to output, data setup
time and hold times, and clock width, and
maximum clock frequency
SDn or RDn
VM
trec
CPn
SF00603
Waveform 3. Recovery time for set or reset to output
VM
RDn
VM
Qn
VM
tPLH
Qn
tw(L)
tPHL
tPLH
SDn
VM
tw(L)
SF00050
Waveform 2. Propagation delay for set and reset to output,
set and reset pulse width
Qn, Qn
VM
tsk(o)
Qn, Qn
SF00590
Waveform 4. Output skew
NOTES:
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
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