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參數(shù)資料
| 型號(hào)： | 935049500602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)移位寄存器 |
| 英文描述： | F/FAST SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, SOT-38-4, DIP-16 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 151K |
| 代理商： | 935049500602 |
file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/N74F195AD.html
Product Information
74F195A; 4-bit
parallel-access shift
register
Information as of 2003-04-22
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topGeneral description
The 74F195A is a 4-Bit Parallel Access Shift Register and its functional characteristics are indicated in the
Logic Diagram and Function Table. This device is useful in a variety of shifting, counting and storage
applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds.
The 74F195A operates in two primary modes: shift right (Q0
→Q1) and parallel load, which are controlled by
the state of the Parallel Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J and K inputs when
the PE input is High, and is shifted one bit in the direction Q0
→Q1→Q2→Q3 following each Low-to-High
clock transition.
The J and K inputs provide the flexibility of the J-K type input for special applications, and by tying the two
together the simple D-type input is made for general applications.
The device appears as four common clocked D flip-flops when the PE input is Low. After the Low-to-High
clock transition, data on the parallel inputs (D0–D3) is transferred to the respective Q0–Q3 outputs. Shift left
operation (Q3–Q2) can be achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE input Low.
All parallel and serial data transfers are synchronous, occurring after each Low-to-High clock transition. The
74F195A utilizes edge-triggering, therefore there is no restriction on the activity of the J, K, Dn, and PE inputs
for logic operation, other than the set-up and hold time requirements.
A Low on the asynchronous Master Reset (MR) input sets all Q outputs Low, independent of any other input
condition.
topFeatures
q
Shift right and parallel load capability
q
J – K (D) inputs to first stage
q
Complement output from last stage
q
Asynchronous Master Reset
q
Diode inputs
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