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參數(shù)資料
| 型號： | 935049500602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)移位寄存器 |
| 英文描述： | F/FAST SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, SOT-38-4, DIP-16 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 151K |
| 代理商： | 935049500602 |
Philips Semiconductors
Product specification
74F195A
4-bit parallel-access shift register
2
1996 Mar 12
853-0024 16555
FEATURES
Shift right and parallel load capability
J – K (D) inputs to first stage
Complement output from last stage
Asynchronous Master Reset
Diode inputs
DESCRIPTION
The 74F195A is a 4-Bit Parallel Access Shift Register and its
functional characteristics are indicated in the Logic Diagram and
Function Table. This device is useful in a variety of shifting, counting
and storage applications. It performs serial, parallel, serial to
parallel, or parallel to serial data transfers at very high speeds.
The 74F195A operates in two primary modes: shift right (Q0
→Q1)
and parallel load, which are controlled by the state of the Parallel
Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J
and K inputs when the PE input is High, and is shifted one bit in the
direction Q0
→Q1→Q2→Q3 following each Low-to-High clock
transition.
The J and K inputs provide the flexibility of the J-K type input for
special applications, and by tying the two together the simple D-type
input is made for general applications.
The device appears as four common clocked D flip-flops when the
PE input is Low. After the Low-to-High clock transition, data on the
parallel inputs (D0–D3) is transferred to the respective Q0–Q3
outputs. Shift left operation (Q3–Q2) can be achieved by tying the
Qn outputs to the Dn-1 inputs and holding the PE input Low.
All parallel and serial data transfers are synchronous, occurring after
each Low-to-High clock transition. The 74F195A utilizes
edge-triggering, therefore there is no restriction on the activity of the
J, K, Dn, and PE inputs for logic operation, other than the set-up and
hold time requirements.
A Low on the asynchronous Master Reset (MR) input sets all Q
outputs Low, independent of any other input condition.
PIN CONFIGURATION
16
15
14
13
12
11
10
7
6
5
4
3
2
1
VCC
Q3
CP
Q3
Q2
Q0
Q1
MR
J
D3
D0
D1
D2
9
8
GND
PE
SF00757
K
TYPE
TYPICAL fMAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F195A
180MHz
40mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
PKG. DWG. #
16-pin plastic DIP
N74F195AN
SOT 38-4
16-pin plastic SO
N74F195AD
SOT 109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE HIGH/LOW
D0 D3
Data inputs
74F195
1.0/0.033
20
A/20A
D0–D3
Data inputs
74F195A
1.0/1.0
20
A/0.6mA
JK
J K orDtype serial inputs
74F195
1.0/0.033
20
A/20A
J, K
J-K or D type serial inputs
74F195A
1.0/1.0
20
A/0.6mA
CP
Clock Pulse input (active rising edge)
74F195
1.0/0.033
20
A/20A
CP
Clock Pulse input (active rising edge)
74F195A
1.0/1.0
20
A/0.6mA
MR
Master Reset input (active Low)
74F195
2.0/0.066
40
A/40A
MR
Master Reset input (active Low)
74F195A
1.0/1.0
20
A/0.6mA
Q0–Q3,
Q3
Data outputs
50/33
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20
A in the High state and 0.6mA in the Low state.
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