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參數(shù)資料
| 型號(hào)： | 935067520602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, OCTAL 1-BIT TRANSCEIVER, TRUE OUTPUT, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 82K |
| 代理商： | 935067520602 |
Philips Semiconductors
Product specification
74ABT853
8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)
1995 Sep 06
5
AC CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500
LIMITS
SYMBOL
PARAMETER
WAVEFORMS
Tamb = +25oC
VCC = +5.0V
Tamb = –40 to +85oC
VCC = +5.0V ±10%
UNIT
Min
Typ
Max
Min
Max
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
4
1.2
1.0
3.4
2.6
4.8
4.0
1.2
1.0
5.3
4.5
ns
tPLH
tPHL
Propagation delay
An to PARITY
1, 4
2.1
2.5
7.4
9.5
9.7
2.1
2.5
11.2
11.0
ns
tPLH
tPHL
Propagation delay
OEA to PARITY
1, 4
1.8
2.3
6.6
6.7
8.5
8.6
1.8
2.3
10.5
10.0
ns
tPLH
Propagation delay
CLEAR to ERROR
3
1.0
3.6
5.5
1.0
6.2
ns
tPLH
tPHL
Propagation delay
ENABLE to ERROR
4
1.8
3.8
4.5
5.1
5.8
1.8
6.0
6.6
ns
tPLH
tPHL
Propagation delay
Bn or PARITY to ERROR
1, 4
2.0
3.0
7.9
9.0
10.1
11.5
2.0
3.0
11.7
12.8
ns
tPZH
tPZL
Output enable time
OEA to An or OEB to Bn, PARITY
2, 5
1.0
2.1
3.2
4.1
5.1
5.8
1.0
2.1
6.2
6.7
ns
tPHZ
tPLZ
Output disable time
OEA to An or OEB to Bn, PARITY
2, 5
3.1
3.2
5.1
5.6
7.3
7.2
3.1
3.2
7.9
8.1
ns
AC SETUP REQUIREMENTS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500
LIMITS
SYMBOL
PARAMETER
WAVEFORMS
Tamb = +25oC
VCC = +5.0V
Tamb = –40 to +85oC
VCC = +5.0V ±10%
UNIT
MIN
TYP
MIN
ts(H)
ts(L)
Setup time, High or Low
Bn or PARITY to ENABLE
6
8.5
6.5
3.6
8.5
ns
th(H)
th(L)
Hold time, High or Low
Bn or PARITY to ENABLE
6
0.0
–3.4
–6.3
0.0
ns
ts(H)
Setup time, High
CLEAR to ENABLE
6
2.0
–1.6
2.0
ns
th(L)
Hold time, Low
CLEAR to ENABLE
6
3.0
1.8
3.0
ns
tw(L)
Pulse width, Low
CLEAR
3
3.5
1.0
3.5
ns
tw(L)
Pulse width, Low
ENABLE
6
4.0
2.5
4.0
ns
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