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參數(shù)資料
| 型號： | 935085450112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AB, SOT-108-1, SO-14 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 100K |
| 代理商： | 935085450112 |
Philips Semiconductors
Product specification
74F50728
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
September 14, 1990
4
characteristics are greatly improved over using two separate flops
that are cascaded. The pin compatibility with the 74F74 allows for
plug–in retrofitting of previously designed systems.
Because the probability of failure of the 74F50728 is so remote, the
metastability characteristics of the part were empirically determined
based on the characteristics of its sister part, the 74F5074. The
table below shows the 74F5074 metastability characteristics.
Having determined the T0 and τ of the flop, calculating the mean
time between failures (MTBF) for the 74F50728 is simple. It is,
however, somewhat different than calculating MTBF for a typical part
because data requires two clock pulses to transit from the input to
the output. Also, in this case a failure is considered of the output
beyond the normal propagation delay.
Suppose a designer wants to use the flop for synchronizing
asynchronous data that is arriving at 10MHz (as measured by a
frequency counter), and is using a clock frequency of 50MHz. He
simply plugs his number into the equation below:
MTBF = e(t’/t)/TofCfI
In this formula, fC is the frequency of the clock, fI is the average
input event frequency, and t’ is the period of the clock input (20
nanoseconds). In this situation the fI will be twice the data
frequency of 20 MHz because input events consist of both of low
and high data transitions. From Fig. 2 it is clear that the MTBF is
greater than 1041 seconds. Using the above formula the actual
MTBF is 2.23 X 1042 seconds or about 7 X 1034 years.
TYPICAL VALUES FOR
τ AND T0 AT VARIOUS VCCS AND TEMPERATURES
Tamb = 0°C
Tamb = 25°C
Tamb = 70°C
τ
T0
τ
T0
τ
T0
VCC = 5.5V
125ps
1.0 X 109 sec
138ps
5.4 X 106 sec
160ps
1.7 X 105 sec
VCC = 5.0V
115ps
1.3 X 1010 sec
135ps
9.8 X 106 sec
167ps
3.9 X 104 sec
VCC = 4.5V
115ps
3.4 X 1013 sec
132ps
5.1 X 108 sec
175ps
7.3 X 104 sec
MEAN TIME BETWEEN FAILURES VERSUS DATA FREQUENCY AT VARIOUS CLOCK FREQUENCY
1070
1060
1050
1040
1030
1020
1010
1000
1K
100K
10M
Data frequency (Hz)
Mean time
between failures
(seconds)
Clock = 40MHz
Clock = 50MHz
Clock = 650MHz
Clock = 70MHz
Clock = 80MHz
Clock = 100MHz
1 billion years
NOTE: VCC = 5V, Tamb = 25°C, τ =135ps, To = 9.8 X 108 sec
SF00610
Figure 2.
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