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參數資料
| 型號： | 935089010518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數： | 37/112頁 |
| 文件大小： | 693K |
| 代理商： | 935089010518 |
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1996 Jun 27
30
Philips Semiconductors
Product specication
8-bit microcontroller with on-chip CAN
P8xC592
13.5
Control Segment and Message Buffer
description
The CAN-controller appears to the CPU as a
memory-mapped peripheral, guaranteeing the
independent operation of both parts.
13.5.1
ADDRESS ALLOCATION
The address area of the CAN-controller consists of the
Control Segment and the message buffers. The Control
Segment is programmed during an initialization down-load
in order to configure communication parameters (e.g. bit
timing). The communication over the CAN-bus is also
controlled via this segment by the CPU. A message which
is to be transmitted, must be written to the Transmit Buffer.
After a successful reception the CPU may read the
message from the Receive Buffer and then release it for
further use.
13.5.2
CONTROL SEGMENT LAYOUT
The exchange of status, control and command signals
between the CPU and the CAN-controller is performed in
the control segment. The layout of this segment is shown
in Fig.15. After an initial down-load, the contents of the
registers Acceptance Code, Acceptance Mask,
Bus Timing 0, Bus Timing 1 and Output Control should not
be changed. These registers may only be accessed when
the Reset Request bit in the Control Register is set HIGH
(see Tables 30, 31 and 32).
handbook, full pagewidth
ADDRESS
0
control segment
MGA160 - 1
CONTROL
descriptor
data field
transmit buffer
descriptor
data field
receive buffer 0 or 1
1
COMMAND
2
STATUS
3
INTERRUPT
4
ACCEPTANCE CODE
5
ACCEPTANCE MASK
6
BUS TIMING 0
7
BUS TIMING 1
8
OUTPUT CONTROL
9
TEST
10
IDENTIFIER,
11
RTR BIT,
DATA LENGTH CODE
12
BYTE 1
13
BYTE 2
14
BYTE 3
15
BYTE 4
16
BYTE 5
17
BYTE 6
18
BYTE 7
19
BYTE 8
20
14H
15H
16H
11H
12H
13H
17H
18H
19H
1AH
1BH
1CH
1DH
IDENTIFIER,
21
RTR BIT,
DATA LENGTH CODE
22
BYTE 1
23
BYTE 2
24
BYTE 3
25
BYTE 4
26
BYTE 5
27
BYTE 6
28
BYTE 7
29
BYTE 8
IDENTIFIER,
RTR BIT,
DATA LENGTH CODE
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
BYTE 8
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0CH
0DH
0EH
0FH
10H
0BH
Fig.15 CAN-controller internal address allocation.
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