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參數(shù)資料
| 型號： | 935089010518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 60/112頁 |
| 文件大?。?/td> | 693K |
| 代理商： | 935089010518 |
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1996 Jun 27
51
Philips Semiconductors
Product specication
8-bit microcontroller with on-chip CAN
P8xC592
13.5.16 AUTO ADDRESS INCREMENT
With the Auto Address Increment mode a fast stack-like
reading and writing of CAN-controller internal registers is
provided. If the bit CANADR.5 (AutoInc) is HIGH, the
content of CANADR is incremented automatically after any
read or write access to CANDAT. For instance, loading a
message into the Transmit Buffer can be done by writing
2AH into CANADR and then moving byte by byte of the
message to CANDAT. Incrementing CANADR beyond
XX111111B resets the bit CANADR.5 (AutoInc)
automatically (CANADR = XX000000B).
13.5.17 HIGH SPEED DMA
The DMA-logic allows you to transfer a complete message
(up to 10 bytes) between CAN-controller and MAIN RAM
in 2 instruction cycles at maximum; up to 4 bytes are
transferred in 1 instruction cycle. The performance of the
CPU is strongly enhanced because this very fast transfer
is carried out in the background.
A DMA transfer is achieved by first writing the RAM
address (00H to FFH) into CANSTA and then setting the
TX- or RX-Buffer address in CANDR and the bit
CANADR.7 (DMA) simultaneously; the RAM address
points to the location of the first byte to be transferred.
Setting the DMA bit causes an automatic evaluation of the
Data Length Code and then the transfer; for a TX-DMA
transfer the Data Length Code is expected at the location
‘RAM address +1’.
In order to program a TX-DMA transfer the value 8AH
(address 10) has to be written into CANADR. Then a
complete message, consisting of the 2-byte Descriptor
and the Data Field (0 to 8 bytes), starting at location
‘RAM address’ is transferred to the TX-Buffer.
The RX-DMA transfer is very versatile. By writing a value
in the range of 94H (address 20) up to 9DH (address 29)
into CANADR the whole or a part of the received message,
starting at the specified address, is transferred to the
internal Data Memory. This allows e.g. to transfer the bytes
of the Data Field only.
After a successful DMA transfer the DMA-bit is reset.
During a DMA transfer the CPU can process the next
instruction. However, an access to the Data Memory,
CANADR, CANDAT, CANCON or CANSTA is not allowed.
After having set the DMA-bit, every interrupt is disabled
until the end of the transfer. Note, that disadvantageous
programming may lead to an interrupt response time of at
most 10 instruction cycles. The shortest interrupt response
time is achieved by using 2 consecutive 1-cycle
instructions directly after setting the DMA-bit.
During the reset state (bit Reset Request is HIGH) a DMA
transfer is not possible.
13.5.18 BUS TIMING/SYNCHRONIZATION
The Bus Timing Logic (BTL) monitors the serial bus-line
via the on-chip input comparator and performs the
following functions (see Section 13.4):
Monitors the serial bus-line level
Adjusts the sample point, within a bit period
(programmable)
Samples the bus-line level using majority logic
(programmable, 1 or 3 samples)
Synchronization to the bit stream:
– hard synchronization at the start of a message
– resynchronization during transfer of a message.
The configuration of the BTL is performed during the
initialization of the CAN-controller. The BTL uses the
following three registers:
Control Register (Sync)
Bus Timing Register 0
Bus Timing Register 1.
13.5.19 BIT TIMING
A bit period is built up from a number of system clock
cycles (tSCL), see Section 13.5.9.
One bit period is the result of the addition of the
programmable segments TSEG1 and TSEG2 and the
general segment SYNCSEG.
13.5.19.1 Synchronization Segment (SYNCSEG)
The incoming edge of a bit is expected during this state;
this state corresponds to one system clock cycle (1
× tSCL).
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