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參數(shù)資料
| 型號： | 935175820112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 門電路 |
| 英文描述： | LV/LV-A/LVX/H SERIES, QUAD 2-INPUT NAND GATE, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, SOT-108-1, MS-012, SO-14 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 132K |
| 代理商： | 935175820112 |
Philips Semiconductors
Product data
74LV03
Quad 2-input NAND gate
2
2003 Mar 03
FEATURES
Wide operating voltage: 1.0 V to 5.5 V
Optimized for Low Voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC = 2.7 V and VCC = 3.6 V
Typical V
OLP (output ground bounce) < 0.8 V @ VCC = 3.3 V,
Tamb = 25 °C
Typical V
OHV (output VOH undershoot) > 2 V @ VCC = 3.3 V,
Tamb = 25 °C
Level shifter capability
Output capability: standard (open drain)
I
CC category: SSI
DESCRIPTION
The 74LV03 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT03.
The 74LV03 provides the 2-input NAND function.
The 74LV03 has open-drain N-transistor outputs, which are not
clamped by a diode connected to VCC. In the OFF-state, i.e., when
one input is LOW, the output may be pulled to any voltage between
GND and VOmax. This allows the device to be used as a
LOW-to-HIGH or HIGH-to-LOW level shifter. For digital operation
and OR-tied output applications, these devices must have a pull-up
resistor to establish a logic HIGH level.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr =tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPZL/tPLZ
Propagation delay
nA, nB to nY
CL = 15 pF
VCC = 3.3 V
8
ns
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per gate
Notes 1, 2
4
pF
NOTES:
1CPD is used to determine the dynamic power dissipation (PD in W)
PD = CPD × VCC2 × fi × N +Σ (CL × VCC2 × fo)
where:
N = the number of outputs switching;
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ (CL × VCC2 × fo) = sum of the outputs.
2
The condition is VI = GND to VCC
3
The given value of CPD is obtained with : CL = 0 pF and RL = ∞
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
PKG. DWG. #
14-Pin Plastic SO
–40
°C to +125 °C
74LV03D
SOT108-1
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
VCC
3B
3A
3Y
4Y
4B
4A
1A
1B
2Y
1Y
2A
2B
SV00354
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1, 4, 9, 12
1A to 4A
Data inputs
2, 5, 10, 13
1B to 4B
Data inputs
3, 6, 8, 11
1Y to 4Y
Data outputs
7
GND
Ground (0 V)
14
VCC
Positive supply voltage
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