參數(shù)資料
型號: 935177130112
廠商: NXP SEMICONDUCTORS
元件分類: 門電路
英文描述: LV/LV-A/LVX/H SERIES, TRIPLE 3-INPUT NAND GATE, PDSO14
封裝: 3.90 MM, PLASTIC, SOT-108-1, MS-012, SO-14
文件頁數(shù): 3/9頁
文件大小: 135K
代理商: 935177130112
Philips Semiconductors
Product data
74LV10
Triple 3-input NAND gate
2003 Mar 04
3
LOGIC SYMBOL (IEEE/IEC)
5
SV00418
1
2
12
4
6
8
9
10
11
13
&
3
LOGIC SYMBOL
1C
1A
13
1
1B
2
2C
2A
5
3
2B
4
3C
3A
11
9
3B
10
SV00417
2Y
3Y
6
8
12
1Y
LOGIC DIAGRAM (ONE GATE)
SV00419
A
B
C
Y
FUNCTION TABLE
INPUTS
OUTPUTS
nA
nB
nC
nY
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
NOTES:
H = HIGH voltage level
L = LOW voltage level
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP.
MAX
UNIT
VCC
DC supply voltage
See Note1
1.0
3.3
3.6
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
Tamb
Operating ambient temperature range in free air
See DC and AC
characteristics
–40
+85
+125
°C
VCC = 1.0 V to 2.0 V
500
ns/V
tr, tf
Input rise and fall times
VCC = 2.0 V to 2.7 V
200
ns/V
VCC = 2.7 V to 3.6 V
100
ns/V
NOTE:
1. The LV is guaranteed to function down to VCC = 1.0 V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2 V to
VCC = 3.6 V.
相關PDF資料
PDF描述
935177130118 LV/LV-A/LVX/H SERIES, TRIPLE 3-INPUT NAND GATE, PDSO14
935178880118 ABT SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24
935155060112 ABT SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDIP24
935155040118 ABT SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24
935178880112 ABT SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24
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