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參數(shù)資料
| 型號： | 935177130118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 門電路 |
| 英文描述： | LV/LV-A/LVX/H SERIES, TRIPLE 3-INPUT NAND GATE, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, SOT-108-1, MS-012, SO-14 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 135K |
| 代理商： | 935177130118 |
Philips Semiconductors
Product data
74LV10
Triple 3-input NAND gate
2
2003 Mar 04
FEATURES
Optimized for Low Voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC = 2.7 V and VCC = 3.6 V
Typical V
OLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25 °C.
Typical V
OHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
Tamb = 25 °C.
Output capability: standard
I
CC category: SSI
DESCRIPTION
The 74LV10 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT10.
The 74LV10 provides the 3-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
nA, nB, nC to nY
CL = 15 pF;
VCC = 3.3 V
9
ns
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per gate
See Notes 1 and 2
12
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in W)
PD = CPD × VCC2 × fi × N + Σ (CL × VCC2 × fo) where:
N = number of outputs switching;
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ (CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
PKG. DWG. #
14-Pin Plastic SO
–40
°C to +125 °C
74LV10D
SOT108-1
PIN CONFIGURATION
SV00416
1
2
3
4
5
6
7
1A
1B
2A
2B
2C
2Y
GND
V
CC
1C
1Y
3C
3B
3A
3Y
14
13
12
11
10
9
8
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1, 3, 9
1A – 3A
Data inputs
2, 4, 10
1B – 3B
Data inputs
7
GND
Ground (0 V)
12, 6, 8
1Y – 3Y
Data outputs
13, 5, 11
1C – 3C
Data inputs
14
VCC
Positive supply voltage
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