參數(shù)資料
型號： 935177130118
廠商： NXP SEMICONDUCTORS
元件分類： 門電路
英文描述： LV/LV-A/LVX/H SERIES, TRIPLE 3-INPUT NAND GATE, PDSO14
封裝： 3.90 MM, PLASTIC, SOT-108-1, MS-012, SO-14
文件頁數(shù)： 5/9頁
文件大?。?/td> 135K
代理商： 935177130118
Philips Semiconductors
Product data
74LV10
Triple 3-input NAND gate
2003 Mar 04
5
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 1 k
CONDITION
LIMITS
SYMBOL
PARAMETER
WAVEFORM
CONDITION
–40
°C to +85 °C
–40
°C to +125 °C
UNIT
VCC(V)
MIN
TYP1
MAX
MIN
MAX
1.2
55
t
/
Propagation delay
Figure 1 2
2.0
19
36
44
ns
tPHL/PLH
gy
nA, nB, nC to nY
Figure 1, 2
2.7
14
26
33
ns
3.0 to 3.6
102
21
26
NOTES:
1. Unless otherwise stated, all typical values are measured at Tamb = 25 °C.
2. Typical values are measured at VCC = 3.3 V.
AC WAVEFORMS
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V;
VOL and VOH are the typical output voltage drop that occur with the
output load.
SV00420
VM
nA, nB, nC
INPUT
nY OUTPUT
VM
t PLH
t PHL
GND
VI
VOL
VOH
Figure 1. Input (nA, nB, nC) to output (nY) propagation delays.
TEST CIRCUIT
PULSE
GENERATOR
RT
VI
D.U.T.
VO
CL
RL = 1k
VCC
Test Circuit for switching times
DEFINITIONS
VCC
VI
< 2.7V
VCC
TEST
tPLH/tPHL
RT = Termination resistance should be equal to ZOUT of pulse generators.
50pF
SV00901
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
2.7–3.6V
2.7V
Figure 2. Load circuitry for switching times.
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