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參數(shù)資料
| 型號： | 935178870118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-355-1, TSSOP1-24 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大小： | 123K |
| 代理商： | 935178870118 |
Philips Semiconductors
Product data
74ABT648
Octal bus transceiver/register, inverting (3-State)
2002 Dec 13
6
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = +25 °C
Tamb = –40 °C
to +85
°C
UNIT
Min
Typ
Max
Min
Max
VIK
Input clamp voltage
VCC = 4.5 V; IIK = –18 mA
–0.9
–1.2
V
VCC = 4.5 V; IOH = –3 mA; VI = VIL or VIH
2.5
3.2
2.5
V
VOH
HIGH-level output voltage
VCC = 5.0 V; IOH = –3 mA; VI = VIL or VIH
3.0
3.7
3.0
V
VCC = 4.5 V; IOH = –32 mA; VI = VIL or VIH
2.0
2.3
2.0
V
VRST
Power-up output low
voltage3
VCC = 5.5 V; IO = 1 mA; VI = GND or VCC
0.13
0.55
V
VOL
LOW-level output voltage
VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH
0.42
0.55
V
I
OFF
Power-off leakage current
VCC = 0.0 V; VI or VO ≤ 4.5 V
±5.0
±100
A
I
PU/
I
PD
Power-up/down 3-State
output current4
VCC = 2.1 V; VO = 0.5 V; VI = GND or VCC;
VOE = Don’t care
±5.0
±50
A
II
Input leakage
Control pins
VCC = 5.5 V; VI = GND or 5.5 V
±0.01
±1.0
A
g
current
Data pins
VCC = 5.5 V; VI = GND or 5.5 V
±5
±100
A
IIH + IOZH
3-State output HIGH current
VCC = 5.5 V; VO = 2.7 V; VI = VIL or VIH
5.0
50
A
IIL + IOZL
3-State output LOW current
VCC = 5.5 V; VO = 0.5 V; VI = VIL or VIH
–5.0
–50
A
I
CEX
Output HIGH leakage current
VCC = 5.5 V; VO = 5.5 V; VI = GND or VCC
5.0
50
A
IO
Output current1
VCC = 5.5 V; VO = 2.5 V
–50
–65
–180
–50
–180
mA
ICCH
VCC = 5.5 V; Outputs HIGH,
VI = GND or VCC
110
250
A
ICCL
Quiescent supply current
VCC = 5.5 V; Outputs LOW,
VI = GND or VCC
20
30
mA
ICCZ
VCC = 5.5 V; Outputs 3-State;
VI = GND or VCC
110
250
A
ICC
Additional supply current per
input pin2
VCC = 5.5 V; one input at 3.4 V,
other inputs at VCC or GND; VCC = 5.5 V
0.3
1.5
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4 V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 msec. From VCC = 2.1 to VCC = 5 V ± 10% a
transition time of up to 100
sec is permitted.
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