參數(shù)資料
型號： 935189060112
廠商： NXP SEMICONDUCTORS
元件分類： 計(jì)數(shù)器
英文描述： HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDSO16
封裝： SOT-403-1, TSSOP-16
文件頁數(shù)： 7/11頁
文件大小： 132K
代理商： 935189060112
December 1990
5
Philips Semiconductors
Product specication
Dual decade ripple counter
74HC/HCT390
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL =50pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85 40 to +125
min.
typ.
max. min. max. min.
max.
tPHL/ tPLH
propagation delay
nCP0 to nQ0
47
17
14
145
29
25
180
36
31
220
44
38
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
nCP1 to nQ1
50
18
14
155
31
26
195
39
33
235
47
40
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
nCP1 to nQ2
74
27
22
210
42
36
265
53
45
315
63
54
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
nCP1 to nQ3
50
18
14
155
31
26
195
39
33
235
47
40
ns
2.0
4.5
6.0
Fig.6
tPHL
propagation delay
nMR to nQn
52
19
15
165
33
28
205
41
35
250
50
43
ns
2.0
4.5
6.0
Fig.7
tTHL/ tTLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.6
tW
clock pulse width
nCP0, nCP1
80
16
14
19
7
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
tW
master reset pulse width
HIGH
80
17
14
28
10
8
105
21
18
130
26
22
ns
2.0
4.5
6.0
Fig.7
trem
removal time
nMR to nCPn
75
15
13
22
8
6
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.7
fmax
maximum clock pulse
frequency
nCP0, nCP1
6.0
30
35
20
60
71
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.6
相關(guān)PDF資料
PDF描述
935189060118 HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDSO16
935189930112 HCT SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDSO16
933715200653 HCT SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDSO16
933670460112 HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16
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