參數資料
型號： 935189060112
廠商： NXP SEMICONDUCTORS
元件分類： 計數器
英文描述： HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDSO16
封裝： SOT-403-1, TSSOP-16
文件頁數： 8/11頁
文件大?。?/td> 132K
代理商： 935189060112
December 1990
6
Philips Semiconductors
Product specication
Dual decade ripple counter
74HC/HCT390
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (
ICC) for a unit load of 1 is given in the family specifications.
To determine
ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr =tf = 6 ns; CL =50pF
INPUT
UNIT LOAD COEFFICIENT
nCP0
nCP1, nMR
0.45
0.60
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
WAVEFORMS
+25
40 to +85 40 to +125
min.
typ.
max. min. max. min.
max.
tPHL/ tPLH
propagation delay
nCP0 to nQ0
21
34
43
51
ns
4.5
Fig.6
tPHL/ tPLH
propagation delay
nCP1 to nQ1
22
38
48
57
ns
4.5
Fig.6
tPHL/ tPLH
propagation delay
nCP1 to nQ2
30
51
64
77
ns
4.5
Fig.6
tPHL/ tPLH
propagation delay
nCP1 to nQ3
22
38
48
57
ns
4.5
Fig.6
tPHL
propagation delay
nMR to nQn
21
36
45
54
ns
4.5
Fig.7
tTHL/ tTLH
output transition time
7
15
19
22
ns
4.5
Fig.6
tW
clock pulse width
nCP0, nCP1
18
8
23
27
ns
4.5
Fig.6
tW
master reset pulse width
HIGH
17
10
21
26
ns
4.5
Fig.7
trem
removal time
nMR to nCPn
15
8
19
22
ns
4.5
Fig.7
fmax
maximum clock pulse
frequency
nCP0, nCP1
27
55
22
18
MHz
4.5
Fig.6
相關PDF資料
PDF描述
935189060118 HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDSO16
935189930112 HCT SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDSO16
933715200653 HCT SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDSO16
933670460112 HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16
933715380112 HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
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