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參數(shù)資料
| 型號： | 935189070112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16 |
| 文件頁數(shù)： | 13/25頁 |
| 文件大?。?/td> | 178K |
| 代理商： | 935189070112 |
20
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
6.4
Starting
6.4.1
Starting from Reset
The internal reset is immediately asserted when a reset source goes active. The internal reset is kept asserted until
the reset source is released and the start-up sequence is completed. The start-up sequence includes three steps,
as follows.
1.
The first step after the reset source has been released consists of the device counting the reset start-up
time. The purpose of this reset start-up time is to ensure that supply voltage has reached sufficient levels.
The reset start-up time is counted using the internal 128 kHz oscillator. See Table 6-1 for details of reset
start-up time.
Note that the actual supply voltage is not monitored by the start-up logic. The device will count until the
reset start-up time has elapsed even if the device has reached sufficient supply voltage levels earlier.
2.
The second step is to count the oscillator start-up time, which ensures that the calibrated internal oscillator
has reached a stable state before it is used by the other parts of the system. The calibrated internal oscil-
lator needs to oscillate for a minimum number of cycles before it can be considered stable. See Table 6-1
for details of the oscillator start-up time.
3.
The last step before releasing the internal reset is to load the calibration and the configuration values from
the Non-Volatile Memory to configure the device properly. The configuration time is listed in Table 6-1.
Notes:
1. After powering up the device or after a reset the system clock is automatically set to calibrated internal 8 MHz oscil-
lator, divided by 8
6.4.2
Starting from Power-Down Mode
When waking up from Power-Down sleep mode, the supply voltage is assumed to be at a sufficient level and only
the oscillator start-up time is counted to ensure the stable operation of the oscillator. The oscillator start-up time is
counted on the selected main clock, and the start-up time depends on the clock selected. See Table 6-2 for details.
Notes:
1. The start-up time is measured in main clock oscillator cycles.
6.4.3
Starting from Idle / ADC Noise Reduction / Standby Mode
When waking up from Idle, ADC Noise Reduction or Standby Mode, the oscillator is already running and no oscilla-
tor start-up time is introduced.
The ADC is available in ATtiny5/10, only.
Table 6-1.
Start-up Times when Using the Internal Calibrated Oscillator
Reset
Oscillator
Configuration
Total start-up time
64 ms
6 cycles
21 cycles
64 ms + 6 oscillator cycles + 21 system clock cycles (1)
Table 6-2.
Start-up Time from Power-Down Sleep Mode.
Oscillator start-up time
Total start-up time
6 cycles
6 oscillator cycles (1)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 933670290112 | 16 X 4 OTHER FIFO, 120 ns, PDIP16 |
| 935189960118 | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
| 933715220112 | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
| 935189070118 | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
| 935189960112 | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
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