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參數(shù)資料
| 型號： | 935189070112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16 |
| 文件頁數(shù)： | 18/25頁 |
| 文件大?。?/td> | 178K |
| 代理商： | 935189070112 |
25
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
7.3.2
Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering
any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion.
See “Analog to Digital Converter” on page 82 for details on ADC operation.
The ADC is available in ATtiny5/10, only.
7.3.3
Watchdog Timer
If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is
enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this
will contribute significantly to the total current consumption. Refer to “Watchdog Timer” on page 30 for details on
how to configure the Watchdog Timer.
7.3.4
Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing
is then to ensure that no pins drive resistive loads. In sleep modes where the I/O clock (clk
I/O) is stopped, the input
buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed.
In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the
section “Digital Input Enable and Sleep Modes” on page 44 for details on which pins are enabled. If the input buffer
is enabled and the input signal is left floating or has an analog signal level close to V
CC/2, the input buffer will use
excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V
CC/2
on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to
the Digital Input Disable Register (DIDR0). Refer to “DIDR0 – Digital Input Disable Register 0” on page 81 for
details.
7.4
Register Description
7.4.1
SMCR – Sleep Mode Control Register
The SMCR Control Register contains control bits for power management.
Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bits 3:1 – SM2..SM0: Sleep Mode Select Bits 2..0
These bits select between available sleep modes, as shown in Table 7-2.
Bit
765
432
1
0
–
SM2
SM1
SM0
SE
SMCR
Read/Write
R
R/W
Initial Value
0
Table 7-2.
Sleep Mode Select
SM2
SM1
SM0
Sleep Mode
000
Idle
0
1
ADC noise reduction (1)
0
1
0
Power-down
011
Reserved
1
0
Standby
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| 933670290112 | 16 X 4 OTHER FIFO, 120 ns, PDIP16 |
| 935189960118 | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
| 933715220112 | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
| 935189070118 | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
| 935189960112 | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
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