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參數(shù)資料
| 型號： | 935189350112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
| 封裝： | 5.30 MM, PLASTIC, MO-150AC, SOT-338-1, SSOP-16 |
| 文件頁數(shù)： | 11/25頁 |
| 文件大?。?/td> | 178K |
| 代理商： | 935189350112 |
19
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
6.2.3
Internal 128 kHz Oscillator
The internal 128 kHz oscillator is a low power oscillator providing a clock of 128 kHz. The frequency depends on
supply voltage, temperature and batch variations. This clock may be select as the main clock by setting the
CLKMS[1:0] bits in CLKMSR to 0b01.
6.2.4
Switching Clock Source
The main clock source can be switched at run-time using the “CLKMSR – Clock Main Settings Register” on page
21. When switching between any clock sources, the clock system ensures that no glitch occurs in the main clock.
6.2.5
Default Clock Source
The calibrated internal 8 MHz oscillator is always selected as main clock when the device is powered up or has
been reset. The synchronous system clock is the main clock divided by 8, controlled by the System Clock Pres-
caler. The Clock Prescaler Select Bits can be written later to change the system clock frequency. See “System
6.3
System Clock Prescaler
The system clock is derived from the main clock via the System Clock Prescaler. The system clock can be divided
by setting the “CLKPSR – Clock Prescale Register” on page 22. The system clock prescaler can be used to
decrease power consumption at times when requirements for processing power is low or to bring the system clock
within limits of maximum frequency. The prescaler can be used with all main clock source options, and it will affect
the clock frequency of the CPU and all synchronous peripherals.
The System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still
ensuring stable operation.
6.3.1
Switching Prescaler Setting
When switching between prescaler settings, the system clock prescaler ensures that no glitch occurs in the system
clock and that no intermediate frequency is higher than neither the clock frequency corresponding the previous set-
ting, nor the clock frequency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the main clock, which may be faster than
the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were read-
able, and the exact time it takes to switch from one clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock fre-
quency is active. In this interval, two active clock edges are produced. Here, T1 is the previous clock period, and
T2 is the period corresponding to the new prescaler setting.
相關(guān)PDF資料 |
PDF描述 |
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| 933715220118 | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
| 935189350118 | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
| 933714740653 | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
| 933714740652 | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
| 933669660652 | 16 X 4 OTHER FIFO, 600 ns, PDIP16 |
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