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參數(shù)資料
| 型號(hào)： | 935189350112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
| 封裝： | 5.30 MM, PLASTIC, MO-150AC, SOT-338-1, SSOP-16 |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 178K |
| 代理商： | 935189350112 |
16
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
5.3
I/O Memory
The I/O space definition of the ATtiny4/5/9/10 is shown in “Register Summary” on page 148.
All ATtiny4/5/9/10 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed using the LD
and ST instructions, enabling data transfer between the 16 general purpose working registers and the I/O space.
I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. See document
“AVR Instruction Set” and section “Instruction Set Summary” on page 150 for more details. When using the I/O
specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that CBI and SBI instructions will only
operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI
instructions work on registers in the address range 0x00 to 0x1F, only.
The I/O and Peripherals Control Registers are explained in later sections.
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| 933715220118 | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
| 935189350118 | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
| 933714740653 | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
| 933714740652 | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
| 933669660652 | 16 X 4 OTHER FIFO, 600 ns, PDIP16 |
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