參數(shù)資料
型號(hào)： 935189960112
廠商： NXP SEMICONDUCTORS
元件分類： FIFO
英文描述： 16 X 4 OTHER FIFO, 120 ns, PDSO16
封裝： 5.30 MM, PLASTIC, MO-150AC, SOT-338-1, SSOP-16
文件頁(yè)數(shù)： 10/25頁(yè)
文件大?。?/td> 178K
代理商： 935189960112
18
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
6.1.4
ADC Clock – clk
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce
noise generated by digital circuitry. This gives more accurate ADC conversion results.
The ADC is available in ATtiny5/10, only.
6.2
Clock Sources
All synchronous clock signals are derived from the main clock. The device has three alternative sources for the
main clock, as follows:
See Table 6-3 on page 21 on how to select and change the active clock source.
6.2.1
Calibrated Internal 8 MHz Oscillator
The calibrated internal oscillator provides an approximately 8 MHz clock signal. Though voltage and temperature
dependent, this clock can be very accurately calibrated by the user. See Table 16-2 on page 117, Figure 17-39 on
This clock may be selected as the main clock by setting the Clock Main Select bits CLKMS[1:0] in CLKMSR to
0b00. Once enabled, the oscillator will operate with no external components. During reset, hardware loads the cal-
ibration byte into the OSCCAL register and thereby automatically calibrates the oscillator. The accuracy of this
calibration is shown as Factory calibration in Table 16-2 on page 117.
When this oscillator is used as the main clock, the watchdog oscillator will still be used for the watchdog timer and
reset time-out. For more information on the pre-programmed calibration value, see section “Calibration Section” on
6.2.2
External Clock
To use the device with an external clock source, CLKI should be driven as shown in Figure 6-2. The external clock
is selected as the main clock by setting CLKMS[1:0] bits in CLKMSR to 0b10.
Figure 6-2.
External Clock Drive Configuration
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure
stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to
unpredictable behavior. It is required to ensure that the MCU is kept in reset during such changes in the clock
frequency.
EXTERNAL
CLOCK
SIGNAL
CLKI
GND
相關(guān)PDF資料
PDF描述
935189350112 16 X 4 OTHER FIFO, 600 ns, PDSO16
933715220118 16 X 4 OTHER FIFO, 120 ns, PDSO16
935189350118 16 X 4 OTHER FIFO, 600 ns, PDSO16
933714740653 16 X 4 OTHER FIFO, 600 ns, PDSO16
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