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參數(shù)資料
| 型號： | 935196510118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | 7.50 MM, PLASTIC, SO-28 |
| 文件頁數(shù)： | 7/35頁 |
| 文件大?。?/td> | 243K |
| 代理商： | 935196510118 |
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1997 Apr 16
15
Philips Semiconductors
Product specication
8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM
PCD3755A; PCD3755E;
PCD3755F
7.2
EEPROM latches
The four EEPROM latches (EEPROM Latch 0 to 3; Fig.5)
cannot be read by user software. Due to their construction,
the latches can only be preset, but not cleared. Successive
write operations through DATR to the EEPROM latches
actually perform a logical OR with the previously stored
data in EEPROM. The EEPROM latches are reset at the
conclusion of any EEPROM cycle.
7.3
EEPROM ags
The four EEPROM flags (F0 to F3; Fig.5) cannot be
directly accessed by user software. An EEPROM flag is
set as a side-effect when the corresponding EEPROM
latch is written through DATR. The EEPROM flags are
reset at the conclusion of any EEPROM cycle.
7.4
EEPROM macros
The instruction sequence used in an EEPROM access
should be treated as an indivisible entity. Erroneous
programs result if ADDR, DATR, RELR or EPCR are
inadvertently changed during an EEPROM cycle or its
setup. Special care should be taken if the program may
asynchronously divert due to an interrupt. Particularly,
a new access to the EEPROM may only be initiated when
no write, erase or erase/write cycles are in progress.
This can be verified by reading bit EWP (register EPCR).
For write, erase and erase/write cycles, it is assumed that
the Timer 2 Reload Register (RELR) has been loaded with
the appropriate value for a 5 ms delay, which depends on
fxtal (see Table 23). The end of a write, erase or erase/write
cycle will be signalled by a cleared EWP and by a Timer 2
interrupt provided that ET2I = 1 and that the derivative
interrupt is enabled.
7.5
EEPROM access
One read, one write, one erase/write and one erase
access are defined by bits EWP and MC1 to MC3 in the
EPCR register; see Table 10.
Read byte retrieves the EEPROM byte addressed by
ADDR when DATR is read. Read cycles are
instantaneous.
Write and erase cycles take 5 ms, however. Erase/write is
a combination of an erase and a subsequent write cycle,
consequently taking 10 ms.
As their names imply, write page, erase page and
erase/write page are applied to a whole EEPROM page.
Therefore, bits AD0 and AD1 of register ADDR (see
Table 13), defining the byte location within an EEPROM
page, are irrelevant during write and erase cycles.
However, write and erase cycles need not affect all bytes
of the page. The EEPROM flags F0 to F3 (see Fig.5)
determine which bytes within the EEPROM page are
affected by the erase and/or write cycles. A byte whose
corresponding EEPROM flag is zero remains unchanged.
With erase page, a byte is erased if its corresponding
EEPROM flag is set. With write page, data in EEPROM
Latch 0 to 3 (Fig.5) are ORed to the individual page bytes
if and only if the corresponding EEPROM flags are set.
In an erase/write cycle, F0 to F3 select which page bytes
are erased and ORed with the corresponding EEPROM
latches.
ORing, in this event, means that the EEPROM latches are
copied to the selected page bytes.
The described page-wise organization of erase and write
cycles allows up to four bytes to be individually erased or
written within 5 ms. This advantage necessitates a
preparation step, called page setup, before the actual
erase and/or write cycle can be executed.
Page setup controls EEPROM latches and EEPROM
flags. This will be described in the Sections 7.5.1 to 7.5.5.
7.5.1
PAGE SETUP
Page setup is a preparation step required before write
page, erase page and erase/write page cycles.
As previously described, these page operations include
single-byte write, erase and erase/write as a special event.
EEPROM flags F0 to F3 determine which page bytes will
be affected by the mentioned page operations. EEPROM
Latch 0 to 3 must be preset through DATR to specify the
write cycle data to EEPROM and to set the EEPROM flags
as a side-effect. Obviously, the actual preset value of the
EEPROM latches is irrelevant for erase page. Preset of
one, two, three or all four EEPROM latches and the
corresponding EEPROM flags can be performed by
repeatedly defining ADDR and writing to DATR (see
Table 17).
If more than one EEPROM latch must be preset, the
subcounter consisting of AD0 and AD1 can be induced to
auto-increment after every write to DATR, thus stepping
through all EEPROM latches. For this purpose, increment
mode (Table 12) must be selected. Auto-incrementing
stops at EEPROM Latch 3. It is not mandatory to start at
EEPROM Latch 0 as in shown in Table 18.
Note that AD2 to AD6 are irrelevant during page setup.
They will usually specify the intended EEPROM page,
anticipating the subsequent page cycle.
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