參數資料
型號： 935196820112
廠商： NXP SEMICONDUCTORS
元件分類： 門電路
英文描述： LV/LV-A/LVX/H SERIES, DUAL 4-INPUT NAND GATE, PDSO14
封裝： 3.90 MM, PLASTIC, SOT-108-1, MS-012, SO-14
文件頁數： 3/10頁
文件大?。?/td> 136K
代理商： 935196820112
Philips Semiconductors
Product data
74LV20
Dual 4-input NAND gate
2
2003 Mar 10
FEATURES
Optimized for Low Voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC = 2.7 V and VCC = 3.6 V
Typical V
OLP (output ground bounce) < 0.8 V @ VCC = 3.3 V,
Tamb = 25 °C
Typical V
OHV (output VOH undershoot) > 2 V @ VCC = 3.3 V,
Tamb = 25 °C
Output capability: standard
I
CC category: SSI
DESCRIPTION
The 74LV20 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT20.
The 74LV20 provides the 4-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr =tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
nA, nB, nC, nD to nY
CL = 15 pF
VCC = 3.3 V
8
ns
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per gate
Notes 1 and 2
22
pF
NOTES:
1CPD is used to determine the dynamic power dissipation (PD in W)
PD = CPD × VCC2 × fi × N + Σ (CL × VCC2 × fo) where:
N = number of outputs switching;
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ (CL × VCC2 × fo) = sum of the outputs.
2
The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
PKG. DWG. #
14-Pin Plastic SO
–40
°C to +125 °C
74LV20D
SOT108-1
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
VCC
2B
2A
2Y
NC
2D
2C
1A
1B
1Y
NC
1C
1D
SV00360
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1, 9
1A to 2A
Data inputs
2, 10
1B to 2B
Data inputs
3, 11
NC
No connection
4, 12
1C to 2C
Data inputs
5, 13
1D to 2D
Data inputs
6, 8
1Y to 2Y
Data outputs
7
GND
Ground (0 V)
14
VCC
Positive supply voltage
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