參數(shù)資料
型號： 935196820112
廠商： NXP SEMICONDUCTORS
元件分類： 門電路
英文描述： LV/LV-A/LVX/H SERIES, DUAL 4-INPUT NAND GATE, PDSO14
封裝： 3.90 MM, PLASTIC, SOT-108-1, MS-012, SO-14
文件頁數(shù)： 6/10頁
文件大小： 136K
代理商： 935196820112
Philips Semiconductors
Product data
74LV20
Dual 4-input NAND gate
2003 Mar 10
5
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 1 k
SYMBOL
PARAMETER
WAVEFORM
CONDITION
LIMITS
–40 to +85
°C
LIMITS
–40 to +125
°C
UNIT
VCC (V)
MIN
TYP1
MAX
MIN
MAX
1.2
–
50
–
tPHL/tPLH
Propagation delay
Figures 1 2
2.0
–
17
32
–
39
ns
tPHL/tPLH
gy
nA, nB, nC, nD to nY
Figures 1, 2
2.7
–
13
24
–
29
ns
3.0 to 3.6
–
102
19
–
23
NOTE:
1
Unless otherwise stated, all typical values are at Tamb = 25 °C.
2
Typical value measured at VCC = 3.3 V.
AC WAVEFORMS
VM = 1.5 V at VCC ≥ 2.7 V ≤ 3.6 V
VM = 0.5 V * VCC at VCC < 2.7 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI
nA, nB, nC, nD
INPUT
GND
VOH
nY OUTPUT
VOL
VM
tPHL
tPLH
SV00364
VM
Figure 1.Input (nA, nB, nC, nD) to output (nY) propagation
delays.
TEST CIRCUIT
PULSE
GENERATOR
RT
VI
D.U.T.
VO
CL
RL = 1k
VCC
Test Circuit for switching times
DEFINITIONS
VCC
VI
< 2.7V
VCC
TEST
tPLH/tPHL
RT = Termination resistance should be equal to ZOUT of pulse generators.
50pF
SV00901
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
2.7–3.6V
2.7V
Figure 2. Load circuitry for switching times.
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