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參數(shù)資料
| 型號： | 935202220112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | ABT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP1-14 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大小： | 128K |
| 代理商： | 935202220112 |
Philips Semiconductors
Product data
74ABT5074
Synchronizing dual D-type flip-flop
with metastable immune characteristics
2002 Dec 17
3
LOGIC SYMBOL
Q0 Q0 Q1 Q1
56
98
VCC = Pin 14
GND = Pin 7
3
4
1
11
10
13
CP0
SD0
RD0
CP1
SD1
RD1
D0
D1
212
SA00002
IEC/IEEE SYMBOL
4
3
2
1
10
11
12
13
5
6
9
8
S
C1
C2
R
1D
2D
R
SA00003
LOGIC DIAGRAM
VCC = Pin 14
GND = Pin 7
5, 9
6, 8
Q
4, 10
1, 13
3, 11
2, 12
SD
RD
CP
D
SF00048
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
SD
RD
CP
D
Q
MODE
L
H
X
H
L
Asynchronous set
H
L
X
L
H
Asynchronous reset
L
X
L
H
Undetermined*
H
↑
h
H
L
Load “1”
H
↑
l
L
H
Load “0”
H
↑
X
NC
Hold
NOTES:
H = HIGH voltage level
h
= HIGH voltage level one set-up time prior to LOW-to-HIGH
clock transition
L
= LOW voltage level
l
= LOW voltage level one set-up time prior to LOW-to-HIGH
clock transition
NC= No change from the previous set-up
X = Don’t care
↑ = LOW-to-HIGH clock transition
↑ = Not LOW-to-HIGH clock transition
*
= This set-up is unstable and will change when either set or
reset return to the HIGH level
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