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參數(shù)資料
| 型號： | 935206130112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | OT PLD, 35 ns, PDSO20 |
| 封裝： | 4.40 MM, PLASTIC, MO-153AC, SOT-360-1, TSSOP-20 |
| 文件頁數(shù)： | 20/23頁 |
| 文件大?。?/td> | 225K |
| 代理商： | 935206130112 |
Philips Semiconductors
Product specification
PLC18V8Z
Zero standby power
CMOS versatile PAL devices
1997 Aug 08
6
OUTPUT MACRO CELL (OMC)
OE
MUX
1
11
CLK
Q
OE
D
F
00
11
10
01
OUT
MUX
10
00
01
11
F
MUX
00
10
11
01
VCC
OUTPUT
POLARITY
CONTROL
FROM
AND
ARRAY
S
X(n)
DIRECTION CONTROL TERM
TO ALL OMCs
{
AC1n
AC2n
NOTE:
Denotes a programmable cell location.
FROM AND
ARRAY
SP
AR
SP00014
THE OUTPUT MACRO CELL (OMC)
The PLC18V8Z series devices have 8 individually programmable
Output Macro Cells. The 72 AND inputs (or product terms) from the
programmable AND array are connected to the 8 OMCs in groups of
9. Eight of the AND terms are dedicated to logic functions; the ninth
is for asynchronous direction control, which enables/disables the
respective bidirectional I/O pin. Two product terms are dedicated for
the Synchronous Preset and Asynchronous Reset functions.
Each OMC can be independently programmed via 16 architecture
control bits, AC1n and AC2n (one pair per macro cell). Similarly,
each OMC has a programmable output polarity control bit (Xn). By
configuring the pair of architecture control bits according to the
configuration cell table, 4 different configurations may be
implemented. Note that the configuration cell is automatically
programmed based on the OMC configuration.
DESIGN SECURITY
The PLC18V8Z series devices have a programmable security fuse
that controls the access to the data programmed in the device. By
using this programmable feature, proprietary designs implemented
in the device cannot be copied or retrieved.
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