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參數(shù)資料
| 型號(hào)： | 935206130112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | OT PLD, 35 ns, PDSO20 |
| 封裝： | 4.40 MM, PLASTIC, MO-153AC, SOT-360-1, TSSOP-20 |
| 文件頁數(shù)： | 3/23頁 |
| 文件大?。?/td> | 225K |
| 代理商： | 935206130112 |
Philips Semiconductors
Product specification
PLC18V8Z
Zero standby power
CMOS versatile PAL devices
1997 Aug 08
11
AC ELECTRICAL CHARACTERISTICS4
Commercial = 0
°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC < 5.25V;
Industrial = –40
°C ≤ Tamb ≤ +85°C, 4.5V ≤ VCC ≤ 5.5V; R2 = 390
TEST CONDITION1
PLC18V8Z35
(Commercial)
PLC18V8ZI
(Industrial)
SYMBOL
PARAMETER
FROM
TO
R1 ()
CL
(pF)
MIN
MAX
MIN
MAX
UNIT
Pulse width
tCKP
Clock period
(Minimum tIS + tCKO)
CLK +
200
50
47
57
ns
tCKH
Clock width High
CLK +
CLK –
200
50
20
25
ns
tCKL
Clock width Low
CLK –
CLK +
200
50
20
25
ns
tARW
Async reset pulse width
I
±, F±
I +, F +
35
40
ns
Hold time
tIH
Input or feedback
data hold time
CLK +
Input
±
200
50
0
ns
Setup time
tIS
Input or feedback
data setup time
I
±, F±
CLK +
200
50
25
30
ns
Propagation delay
tPD
Delay from input
to active output
I
±, F±
F
±
200
50
35
40
ns
tCKO
Clock High to output valid
access Time
CLK +
F
±
200
50
22
27
ns
tOE13
Product term enable to
outputs off
I
±, F±
F
±
Active-High R = 1.5k
Active-Low R = 550
50
35
40
ns
tOD12
Product term disable to
outputs off
I
±, F±
F
±
From VOH R = ∞
From VOL R = 200
5
35
40
ns
tOD22
Pin 11 output disable High
to outputs off
OE –
F
±
From VOH R = ∞
From VOL R = 200
5
25
40
ns
tOE23
Pin 11 output enable to
active output
OE +
F
±
Active-High R = 1.5k
Active-Low R = 550
50
25
30
ns
tARD
Async reset delay
I
±, F±
F +
35
40
ns
tARR
Async reset recovery time
I
±, F±
CLK +
25
30
ns
tSPR
Sync preset recovery time
I
±, F±
CLK +
25
30
ns
tPPR
Power-up reset
VCC +
F +
35
40
ns
Frequency of operation
fMAX
Maximum frequency
I/(tIS + tCKO)
200
50
21
18
MHz
NOTES:
1. Refer also to AC Test Conditions. (Test Load Circuit)
2. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output
voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed.
3. Resistor values of 1.5k and 550
provide 3-State levels of 1.0V and 2.0V, respectively. Output timing measurements are to 1.5V level.
4. Leave all the cells on unused product terms intact (unprogrammed) for all patterns.
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