參數(shù)資料
型號(hào)： 935225410112
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PDIP40
封裝： 0.600 INCH, PLASTIC, DIP-40
文件頁數(shù)： 24/67頁
文件大?。?/td> 400K
代理商： 935225410112
1998 Apr 07
30
Philips Semiconductors
Product specication
8-bit Flash microcontrollers
P89C738; P89C739
13.4
Status of external pins
Table 20 Status of the external pins during Idle and Power-down modes
13.5
Power Control Register (PCON)
Special modes are activated by software via the SFR PCON. PCON is not bit addressable. The reset value of PCON is
00H.
Table 21 Power Control Register (SFR address 87H)
Table 22 Description of PCON bits
Note
1. If logic 1s are written to PD and IDL at the same time, PD takes precedence.
MODE
MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
Idle
internal
HIGH
port data
external
HIGH
oating
port data
address
port data
Power-down
internal
LOW
port data
external
LOW
oating
port data
76543210
SMOD
ARE
RFI
WLE
GF1
GF0
PD
IDL
BIT
SYMBOL
DESCRIPTION
7
SMOD
Double baud rate bit. When set to a logic 1 the baud rate is doubled when Timer 1 is
used to generate baud rate, and the Serial Port is used in Modes 1, 2 or 3.
6
ARE
AUX-RAM enable bit. When set to a logic 1 the AUX-RAM is disabled, so that all
MOVX-instructions access the external data memory.
5
RFI
Reduced Radio Frequency Interference bit. When set to a logic 1 the toggling of the
ALE pin is prohibited. This bit is cleared on reset. See also Chapters 1 “Features”: on
EMC and 6 “Pinning information”: note 2.
4
WLE
Watchdog Load Enable. This ag must be set by software prior to loading the
Watchdog Timer (T3). It is cleared when timer T3 is loaded.
3
GF1
General-purpose ag bit.
2
GF0
1PD(1)
Power-down select. Setting this bit activates the Power-down mode.
0
IDL(1)
Idle mode select. Setting this bit activates the Idle mode.
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